Retiming is an optimization technique for synchronous circuits introduced by Leiserson and Saxe in 1983 [1]. Since then, the retiming concept has not been widely used and followed-up. It is fair to conclude why this powerful retiming algorithm has not been widely used in the logic synthesis tools until recently due to the following issues:
1) Retiming tends to increase area utilization, which was very costly in early ASIC and programmable logic.
2) Bandwidth has not always been an urgent need for implementing a typical design.
3) Limitation of applying retiming algorithm due to different type of registers with complex control signals.
However, in the recent years, designers have been demanding faster and higher bandwidth. Bandwidth has become the most common design bottleneck in network and telecom systems and it has continued to be until now. At the same time, the designs have become more complex and sophisticated. One of the most compelling technologies to apply this proved effectiveness of retiming algorithm is on Field Programmable Gate Arrays (FPGA). In this paper, we present the following facts:
1) How do FPGA synthesis tools implement and utilize retiming functions.
2) Why is FPGA a more suitable target technology for retiming algorithm than others?
How is retiming being integrated with today’s FPGA synthesis flows?
研究FPGA性能优化的可以看看这篇**.
使用retiming提高FPGA性能.pdf
(548.71 KB)
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