AT91SAM9260在SRAM启动问题

只看该作者 · 2011-6-13 14:30

开发环境是KEIL MDK+jlink，下载时出现下面情况：

Load "C:\\Documents and Settings\\hp\\My Documents\\Keil程序\\In SRAM.AXF"
VTarget = 3.235V
Info: TotalIRLen = 4, IRPrint = 0x01
Info: CP15.0.0: 0x41069265: ARM, Architecure 5TEJ
Info: CP15.0.1: 0x1D112112: ICache: 8kB (4*64*32), DCache: 8kB (4*64*32)
Info: Cache type: Separate, Write-back, Format C (WT supported)
Info: RTCK reaction time is approx. 189ns
Info: Auto JTAG speed: Adaptive
Info: J-Link: ARM9 CP15 Settings changed: 50078 from 78, MMU Off, ICache Off, DCache Off
Info: TotalIRLen = 4, IRPrint = 0x01
Info: CP15.0.0: 0x41069265: ARM, Architecure 5TEJ
Info: CP15.0.1: 0x1D112112: ICache: 8kB (4*64*32), DCache: 8kB (4*64*32)
Info: Cache type: Separate, Write-back, Format C (WT supported)
DLL version V4.15n, compiled Jun 18 2010 19:55:09
Firmware: J-Link ARM V7 compiled Jun 30 2009 11:05:27
Hardware: V7.00
Hardware-Breakpoints: 2
Software-Breakpoints: 2048
Watchpoints: 0
Found 1 JTAG device, Total IRLen = 4:
Id of device #0: 0x0792603F
ARM9 identified.
Using adaptive clocking instead of fixed JTAG speed.
Info: TotalIRLen = 4, IRPrint = 0x01
Info: CP15.0.0: 0x41069265: ARM, Architecure 5TEJ
Info: CP15.0.1: 0x1D112112: ICache: 8kB (4*64*32), DCache: 8kB (4*64*32)
Info: Cache type: Separate, Write-back, Format C (WT supported)
Using adaptive clocking instead of fixed JTAG speed.
No Algorithm found for: 00200000H - 00200C37H
Erase skipped!
不知道各位有没有知道是什么原因的，给小弟分析一下，谢谢

只看该作者 · 2011-6-13 14:31

SRAM的初始文件如下：

DEFINE INT  __mac_i;

FUNC void _MapRAMAt0(){

printf ("Changing mapping: RAM mapped to 0 \n");
// Test and set Remap
__mac_i = _RDWORD(0xFFFFEF00);
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
      _WDWORD(0xFFFFEF00,0x03); // toggle remap bits
}
else
{
      printf ("------------------------------- The Remap is done -----------------------------------\n");
}
}

//----------------------------------------------------------------------------
// _InitRSTC()
// Function description
// Initializes the RSTC (Reset controller).
// This makes sense since the default is to not allow user resets, which makes it impossible to
// apply a second RESET via J-Link
//----------------------------------------------------------------------------

FUNC void _InitRSTC() {
_WDWORD(0xFFFFFD08,0xA5000001); // Allow user reset
}

//----------------------------------------------------------------------------
//
//  _PllSetting()
//  Function description
//  Initializes the PMC.
//  1. Enable the Main Oscillator
//  2. Configure PLL
//  3. Switch Master
//----------------------------------------------------------------------------

FUNC void __PllSetting()
{
if ((_RDWORD(0xFFFFFC30)&0x3) != 0 ) {
// Disable all PMC interrupt ( $$ JPP)
// AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
// pPmc->PMC_IDR = 0xFFFFFFFF;
      _WDWORD(0xFFFFFC64,0xFFFFFFFF);
// AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
      _WDWORD(0xFFFFFC14,0xFFFFFFFF);
// Disable all clock only Processor clock is enabled.
      _WDWORD(0xFFFFFC04,0xFFFFFFFE);
// AT91C_PMC_MCKR  ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
      _WDWORD(0xFFFFFC30,0x00000001);
      _sleep_(100);
      // write reset value to PLLA and PLLB
      // AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
      _WDWORD(0xFFFFFC28,0x00003F00);

      // AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
      _WDWORD(0xFFFFFC2C,0x00003F00);
      _sleep_(100);

      printf ( "------------------------------- PLL  Enable -----------------------------------------");
}
else {
   printf( " ********* Core in SLOW CLOCK mode ********* ");
   }
}

//----------------------------------------------------------------------------
//
//    __PllSetting100MHz()
// Function description
//  Set core at 200 MHz and MCK at 100 MHz
//----------------------------------------------------------------------------

FUNC void __PllSetting100MHz()
{
printf( "------------------------------- PLL Set at 100 MHz ----------------------------------");

//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
_WDWORD(0xFFFFFC20,0x00004001);
_sleep_(100);
// AT91C_PMC_MCKR  ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
_WDWORD(0xFFFFFC30,0x00000001);
_sleep_(100);
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
_WDWORD(0xFFFFFC28,0x2060BF09);
_sleep_(100);
// Configure PLLB
_WDWORD(0xFFFFFC2C,0x207C3F0C);
_sleep_(100);
//* AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
_WDWORD(0xFFFFFC30,0x00000102);
   _sleep_(100);
}

//Setup();
__PllSetting();                //* Init PLL
__PllSetting100MHz();
_MapRAMAt0();                   //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
_InitRSTC();
LOAD C:\Documents and Settings\\hp\My Documents\\Keil程序\\at91sam9260-sram.axf INCREMENTAL
PC = 0x200000;
g,main

不知道初始文件是不是有问题

只看该作者 · 2011-8-10 09:33

沙发

AT91SAM9260在SRAM启动问题

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