28335与CAN设备进行通信

只看该作者 · 2018-4-21 13:35

小弟最近在做28335与CAN设备之间的通信，下面是CAN设备的通信协议

第一个疑问：如果波特率一致，然后ID也匹配，那么发送成功以后，是否会把我邮箱的数据送到CAN设备里？

目前的想象是我应该已经成功把我邮箱的数据发送给CAN设备了，但是无法从CAN设备接收数据。

还有一个问题，我的ID设置也与协议不同，但是也成功发送了，这是什么原因呢？

只看该作者 · 2018-4-21 13:38

发送代码

：
void InitECanb(void) // Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanbShadow;

EALLOW; // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.SCB = 1;
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.

ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */

ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANB*/

ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 1 ;          // Set CCR = 1
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

ECanbShadow.CANES.all = ECanbRegs.CANES.all;

do
{
      ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be  cleared..

ECanbShadow.CANBTC.all = 0;

#if (CPU_FRQ_150MHZ)                      // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
   See Note at end of file */
ECanbShadow.CANBTC.bit.BRPREG = 39;
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
#endif
#if (CPU_FRQ_100MHZ)                      // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
   See Note at end of file */
      ECanbShadow.CANBTC.bit.BRPREG = 4;
ECanbShadow.CANBTC.bit.TSEG2REG = 1;
ECanbShadow.CANBTC.bit.TSEG1REG = 6;
#endif

ECanbShadow.CANBTC.bit.SAM = 1;
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 0 ;          // Set CCR = 0
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

ECanbShadow.CANES.all = ECanbRegs.CANES.all;

do
{
      ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs

EDIS;
   ECanbMboxes.MBOX25.MSGID.all = 0x90200010; // Extended Identifier

/* Configure Mailbox under test as a Transmit mailbox */

ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
ECanbShadow.CANMD.bit.MD25 = 0; ///  1：接收邮箱  0：发送邮箱
ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

/* Enable Mailbox under test */

ECanbShadow.CANME.all = ECanbRegs.CANME.all;
ECanbShadow.CANME.bit.ME25 = 1;    ///  1：使能 0：  不使能
ECanbRegs.CANME.all = ECanbShadow.CANME.all;

/* Write to DLC field in Master Control reg */

ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8;

/* Write to the mailbox RAM field */

ECanbMboxes.MBOX25.MDL.all = 0x00000000;
ECanbMboxes.MBOX25.MDH.all = 0x00620000;
//  j=0x01;
}

只看该作者 · 2018-4-21 13:39

while(1)
{
  // for(i=0; i < TXCOUNT; i++)
{

for(t = 0x00;t < 2;t++)
{

   InitECanb();

   ECanbShadow.CANTRS.all = 0;
   ECanbShadow.CANTRS.bit.TRS25 = 1;          // Set TRS for mailbox under test
   ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all;
   kk = 0;
   do
{
   kk = kk + 1;
//    ECanbShadow.CANTRS.all = 0;
   // ECanbShadow.CANTRS.bit.TRS25 = 1;          // Set TRS for mailbox under test
   // ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all;
      ECanbShadow.CANTA.all = ECanbRegs.CANTA.all;
        } while((ECanbShadow.CANTA.bit.TA25 == 0 ) && (kk < 10000)); // Wait for TA5 bit to be set..

      if( kk < 10000) break;
   }
   if(kk<10000) j++;

//    loopcount ++;
// j++;
//  ECanbMboxes.MBOX25.MDL.all = j;
//  ECanbMboxes.MBOX25.MDH.all = j + 1;

   ECanbShadow.CANTA.all = 0;
   ECanbShadow.CANTA.bit.TA25 = 1;               // Clear TA5
   ECanbRegs.CANTA.all = ECanbShadow.CANTA.all;
// delay();


}
}