entity dpram_w_r is
generic (
ADDR_WIDTH : integer := 11;
DATA_WIDTH : integer := 8
);
port (
clka : in std_logic;
ena : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(ADDR_WIDTH-1 downto 0);
dina : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkb : in std_logic;
enb : in std_logic;
addrb : in std_logic_vector(ADDR_WIDTH-1 downto 0);
doutb : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end dpram_w_r;
architecture rtl of dpram_w_r is
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram : ram_type;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : signal is "block_ram" ;
begin
-- dual port block ram inference
process (clka)
begin
if rising_edge(clka) then
if ena = '1' then
if wea = '1' then
ram(to_integer(unsigned(addra))) <= dina;
end if;
end if;
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if enb = '1' then
doutb <= ram(to_integer(unsigned(addrb)));
end if;
end if;
end process;
end rtl;
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