HMC830LatchClr(chanl);
delay_ms(10);
HMC830LatchSet(chanl); //If a rising edge on SEN is detected first HMC Mode is selected.
delay_ms(10); //SEN to SCLK setup time > 8ns
for (i = 0; i < 32; i++) //b.The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low indi cates a Write cycle (/WR).
{
//d,f.Slave shifts the 6 address bits, the 24 data bits in the next 30 rising edges of SCK (2-31).
PLL_REG <<= 1; //首位数据无效，丢掉；最后一位补零凑齐32个时钟周期
clk_830_clr(chanl); //HMC830时钟
if ((PLL_REG & 0x80000000) == 0)
{
data_830_clr(chanl); //HMC830 数据
}
else
{
data_830_set(chanl);
}
delay_us(5); //SDI to SCLK setup time > 3ns
clk_830_set(chanl);
delay_us(5); //SCLK to SDI hold time > 3ns
}
clk_830_clr(chanl); //HMC830时钟
delay_ms(10); //SCK to SEN fall > 10ns
HMC830LatchClr(chanl);
delay_ms(20); //SEN low duration > 20 ns
}
HMC830LatchClr(chanl);
delay_ms(10);
HMC830LatchSet(chanl); //If a rising edge on SEN is detected first HMC Mode is selected.
delay_ms(10); //SEN to SCLK setup time > 8ns
for (i = 0; i < 7; i++) //b. The slave (PLL with Integrated VCO) reads SDI on the 1st rising edge of SCLK after SEN. SDI high initiates the READ cycle (RD)
{
//d. Slave registers the address bits on the next six rising edges of SCLK (2-7).
PLL_REG <<= 1; //首位数据无效，丢掉
clk_830_clr(chanl); //HMC830时钟
if ((PLL_REG & 0x80000000) == 0)
{
data_830_clr(chanl); //HMC830数据
}
else
{
data_830_set(chanl);
}
delay_us(5); //SDI to SCLK setup time > 3ns
clk_830_set(chanl);
delay_us(5); //SCLK to SDI hold time > 3ns
}
clk_830_clr(chanl); //HMC830时钟
data_830_clr(chanl); //HMC830数据
delay_us(5);
PLL_REG = 0x00000000; //读HMC830数据
for (i = 0; i < 24; i++) //f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
{
PLL_REG <<= 1;
clk_830_set(chanl);
delay_us(5); //SCLK to SDO delay > 8.2ns+0.2ns/pF
if (Read_LOCK_830_PLL0())
{
PLL_REG |= 0x00000001; //HMC830数据
}
else
{
PLL_REG &= ~0x00000001; //HMC830数据
}
clk_830_clr(chanl); //HMC830时钟
delay_us(5);
}
clk_830_set(chanl);
delay_us(5);
clk_830_clr(chanl); //HMC830时钟
delay_ms(10); //Recovery Time > 10ns
HMC830LatchClr(chanl); //h. Deassertion of SEN completes the cycle
delay_ms(20); //SEN low duration > 20 ns
for (i = 0; i < 32; i++) //the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
{
clk_830_clr(chanl); //HMC830时钟
if ((PLL_REG & 0x80000000) == 0)
{
data_830_clr(chanl); //HMC830 数据
}
else
{
data_830_set(chanl);
}
delay_us(5); //SDI to SCLK setup time > 3ns
clk_830_set(chanl);
delay_us(5); //SCLK to SDI hold time > 3ns
PLL_REG <<= 1;
}
HMC830LatchClr(chanl);
delay_ms(10); //SEN low duration > 10ns, SCLK 32 Rising Edge to SEN Rising Edge > 10ns
HMC830LatchSet(chanl); //h.Slave registers the SDI data on the rising edge of SEN.
delay_ms(10); //SEN high duration > 10ns
HMC830LatchClr(chanl);
delay_ms(20); //Recovery Time > 20 ns
}
// 1.first SPI cycle to write the desired address to Reg0h[7:3]**********************************************************************
for (i = 0; i < 32; i++) //b.the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
{
clk_830_clr(chanl); //HMC830时钟
if ((PLL_REG & 0x80000000) == 0)
{
data_830_clr(chanl); //HMC830 数据
}
else
{
data_830_set(chanl);
}
delay_us(5); //SDI to SCLK setup time > 3ns
clk_830_set(chanl);
delay_us(5); //SCLK to SDI hold time > 3ns
PLL_REG <<= 1;
}
HMC830LatchClr(chanl);
delay_ms(10); //SCLK 32 Rising Edge to SEN Rising Edge > 10ns
HMC830LatchSet(chanl); //h.Slave registers the SDI data on the rising edge of SEN.
delay_ms(10); //SEN high duration > 10ns
HMC830LatchClr(chanl); //i.Master clears SEN to complete the the address transfer of the two part READ cycle
delay_ms(10); //Recovery Time > 10 ns
// 2.next SPI cycle the desired data will be available on LD_SDO.*******************************************************************************
HMC830LatchSet(chanl); //b. If a rising edge on SCLK is detected first Open mode is selected.
delay_ms(10); //SEN high duration > 10ns
clk_830_clr(chanl); //HMC830时钟
data_830_clr(chanl); //HMC830数据
delay_us(5);
PLL_REG = 0x00000000; //读HMC830数据
for (i = 0; i < 24; i++) //m.Slave places the desired read data(ie. data from the address specified in Reg 00h [7:3] of the first cycle) on LD_SDO
{
PLL_REG <<= 1;
clk_830_set(chanl);
delay_us(5); //SCLK Rising Edge to SDO time > 8.2ns+0.211ns/pF
if (Read_LOCK_830_PLL0())
{
PLL_REG |= 0x00000001; //HMC830数据
}
else
{
PLL_REG &= ~0x00000001; //HMC830数据
}
clk_830_clr(chanl); //HMC830时钟
delay_us(5);
}
for (i = 0; i < 8; i++) //d.Slave shifts the register bits on the next 5 rising edges of SCLK (25-29)
{
//f.Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32)
clk_830_clr(chanl); //HMC830时钟
data_830_clr(chanl); //HMC830 数据
delay_us(5); //SDI to SCLK setup time > 3ns
clk_830_set(chanl);
delay_us(5); //SCLK to SDI hold time > 3ns
}
HMC830LatchClr(chanl);
delay_ms(10); //SCLK 32 Rising Edge to SEN Rising Edge > 10ns
HMC830LatchSet(chanl); //b. If a rising edge on SCLK is detected first Open mode is selected.
delay_ms(10); //SEN high duration > 10ns
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