Microcontrollers and FPGAs often work together in embedded systems. As more functions move into the FPGA, however, debugging the interface between the two devices becomes more difficult. The traditional debugging approach comes from the microcontroller side, which relies on a serial-port printout. This approach adds overhead and may cause timing problems. Furthermore, this approach cannot guarantee uninterrupted and exclusive access to certain addresses because of operating-system multitasking. Thus, a serial-port printout doesn’t accurately describe the actions on the microcontroller/FPGA interface.
Instead, you can approach the problem from the FPGA side using a JTAG (Joint Test Action Group) interface as a communication port. This approach uses the internal logic of the FPGA to capture the read/write transactions on the microcontroller/FPGA interface. This method is nonintrusive because the circuit that captures transactions sits between the microcontroller and the FPGA’s functioning logic and monitors the data without interfering with it. It stores the captured transaction in the FPGA’s RAM resources in real time. You can transfer the data to a PC through the JTAG port’s download cable.
The debugging tool comprises the data-capture circuit, the JTAG communication circuit, and the GUI (graphical user interface)。 The data-capture circuit uses standard HDL (hardware-description language) and instantiates a FIFO (first-in/first-out) buffer in the FPGA. Whenever you read or write to a register, the debugging tool records the corresponding value of the address and data on the bus and stores it in the FIFO buffer. You can retrieve the data through the JTAG’s download cable to the PC (Listing 1 - all listings are provided on subsequent pages or as a downloadable doc file from the links below)。 |