前段時間在21IC上看到有人說SMBUS跟I2C的區別：SMBUS可以自動復位，但是I2C不能。有點將信將疑，昨天翻看了一下SMBUS 2.0 SPEC，發現協議里面有寫他們的區別，不過其中并沒有說到自動復位的問題，主要區別就是電氣特性、電平上面的定義、時序和ACK and NACK的使用方面的，總體上SMBUS要求更高一點。而說到復位，SMBUS支持一個ARP reset，應該是slave address沖突的時候的reset。
Differences between SMBus and I2C
While SMBus is derived from I2C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.
DC specifications for SMBus and I2C
Both I2C and SMBus are capable of operating with mixed devices that have either fixed input levels (such as Smart Batteries) or input levels related to VDD. When mixing devices, the I2C specification defines the VDD to be 5.0 Volt +/- 10% and the fixed input levels to be 1.5 and 3.0 Volts. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed at 0.8 and 2.1 Volts. This SMBus specification allows for bus implementations with VDD ranging from 3 to 5 Volts +/- 10%. SMBus has relaxed the initial requirement for fixed input levels of 0.6 and 1.4 Volts, in order to reduce the cost of SMBus compliant devices. Devices compliant with the 1.0 specification of SMBus will still operate with higher versions of SMBus.
A second difference in the DC parameters between I2C and SMBus is in the power consumption of the low power version of the bus. SMBus low-power electricals are designed to accommodate extremely low power consumption devices, such as the control circuitry within a Smart Battery. These devices have limited current sinking capabilities and a low power consumption bus is essential for maintaining communications without draining the battery of a mobile computer. As a result, SMBus sets more stringent DC requirements than I2C. One of the main differences is the IOL specification for VOL = 0.4 Volts.
SMBus low-power devices are required to sink a minimum of 100 uA as opposed to 3mA specified for I2C devices for the same VOL.
A third difference is in the specification of the maximum leakage current for each device connected to the bus. I2C specifies the maximum leakage current to be 10 uA. SMBus version 1.0 specified maximum leakage current of 1 uA. Version 1.1 of the SMBus specification relaxes the leakage requirements to 5 uA, in order to reduce the cost of testing of SMBus devices.
Finally, SMBus does not specify a maximum bus capacitance. Instead it specifies the IPULLDOWN maximum of 350 uA. Bus capacitance can be calculated taking into consideration the maximum rise time and IPULLDOWN.
The following table lists the main differences among the DC parameters for I2C and SMBus.
Table 10: DC parameter differences between SMBus and I2C
Timing specification differences between SMBus and I2C
There are differences in the timing specifications between I2C and SMBus. As in the case of DC specification, proper understanding of the parameters is needed in order to combine reliably I2C with SMBus devices.
SMBus defines a minimum bus clock frequency FSMB of 10 KHz. I2C does not specify any minimum bus frequency. Besides maintaining effective bus throughput, this SMBus specification parameter can be used as a simple way to detect a bus idle condition (in addition or in lieu of detecting each STOP condition) as well as to implement bit timeout.
SMBus defines a data hold time, the time during which SMBDAT must remain valid from the falling edge of SMBCLK, of 300 nS. I2C defines this hold time as zero.
Maximum clock frequency for SMBus is defined at 100 KHz. I2C provides two modes of operation. The STANDARD MODE up to 100 KHz and the FAST-MODE up to 400 KHz. SMBus defines a clock low time-out, TTIMEOUT of 35 ms. I2C does not specify any timeout limit.
SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. I2C does not have a similar specification.
SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device. Again I2C does not have a similar specification.
SMBus defines both rise and fall time of bus signals. I2C does not.
The SMBus time-out specifications do not preclude I2C devices co-operating reliably on the SMBus. It is the responsibility of the designer to ensure that I2C devices are not going to violate these bus timing parameters.
Other differences
ACK and NACK usage
There are the following differences in the use of the NACK bus signaling:
In I2C, a slave receiver is allowed not to acknowledge the slave address, if for example is unable to receive because it’s performing some real time task. SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable device’s presence on the bus (battery, docking station, etc.)
I2C specifies that a slave device, although it may acknowledge its own address, some time later in the transfer it may decide that it cannot receive any more data bytes. The I2C specifies, that the device may indicate this by generating the not acknowledge on the first byte to follow. Besides to indicate a slave device busy condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This is important because SMBus does
not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
SMBus protocols
Each message transaction on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I2C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and ACPI specifications.
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