关于xlinx 用户base的问题！

只看该作者 · 2011-10-14 16:10

下面的文字大家都很熟悉吧呵呵
我不太懂  帮我指点指点呗！
  我想用4个寄存器来控制8个灯，一个控制2个灯，控制编码用C写应该掌握哪些技术要点？
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
  generic
  (
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH                : integer             := 32;
C_NUM_REG                   : integer             := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
  LED                         : out std_logic_vector(0 to 7);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk                   : in  std_logic;
Bus2IP_Reset                : in  std_logic;
Bus2IP_Addr                   : in  std_logic_vector(0 to 31);
Bus2IP_CS                   : in  std_logic_vector(0 to 0);
Bus2IP_RNW                   : in  std_logic;
Bus2IP_Data                   : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE                   : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE                   : in  std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE                   : in  std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data                   : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck                : out std_logic;
IP2Bus_WrAck                : out std_logic;
IP2Bus_Error                : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
end entity user_logic;
  signal slv_reg0                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel             : std_logic_vector(0 to 3);
  signal slv_reg_read_sel             : std_logic_vector(0 to 3);
  signal slv_ip2bus_data             : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                : std_logic;
  signal slv_write_ack                : std_logic;
begin
  --USER logic implementation added here
  process( Bus2IP_Clk ) is
  begin
  if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
   if Bus2IP_Reset = '1' then
      slv_reg0 <= (others => '0');
      slv_reg1 <= (others => '0');
      slv_reg2 <= (others => '0');
      slv_reg3 <= (others => '0');
   else
      case slv_reg_write_sel is
   when "1000" =>
   LED(0 to 1) <= slv_reg0(0 to 1);
   when "0100" =>
   LED(2 to 3) <= slv_reg1(2 to 3);
   when "0010" =>
   LED(4 to 5) <= slv_reg2(4 to 5);
   when "0001" =>
   LED(6 to 7) <= slv_reg3(6 to 7);
   when others => null;
      end case;
   end if;
end if;
  end process;
  --
  -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
  --                   "1000" C_BASEADDR + 0x0
  --                   "0100" C_BASEADDR + 0x4
  --                   "0010" C_BASEADDR + 0x8
  --                   "0001" C_BASEADDR + 0xC
  --
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack    <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack    <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
   if Bus2IP_Reset = '1' then
      slv_reg0 <= (others => '0');
      slv_reg1 <= (others => '0');
      slv_reg2 <= (others => '0');
      slv_reg3 <= (others => '0');
   else
      case slv_reg_write_sel is
      when "1000" =>
         for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
            if ( Bus2IP_BE(byte_index) = '1' ) then
            slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
            end if;
         end loop;
      when "0100" =>
         for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
            if ( Bus2IP_BE(byte_index) = '1' ) then
            slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
            end if;
         end loop;
      when "0010" =>
         for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
            if ( Bus2IP_BE(byte_index) = '1' ) then
            slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
            end if;
         end loop;
      when "0001" =>
         for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
            if ( Bus2IP_BE(byte_index) = '1' ) then
            slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
            end if;
         end loop;
      when others => null;
      end case;
   end if;
end if;
  end process SLAVE_REG_WRITE_PROC;
  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin
case slv_reg_read_sel is
   when "1000" => slv_ip2bus_data <= slv_reg0;
   when "0100" => slv_ip2bus_data <= slv_reg1;
   when "0010" => slv_ip2bus_data <= slv_reg2;
   when "0001" => slv_ip2bus_data <= slv_reg3;
   when others => slv_ip2bus_data <= (others => '0');
end case;
  end process SLAVE_REG_READ_PROC;
  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
               (others => '0');
  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';
end IMP;

下面的文字大家都很熟悉吧呵呵
我不太懂  帮我指点指点呗！
  我想用4个寄存器来控制8个灯，一个控制2个灯，控制编码用C写应该掌握哪些技术要点？
port
  (
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
  LED                         : out std_logic_vector(0 to 7);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk                   : in  std_logic;
Bus2IP_Reset                : in  std_logic;
Bus2IP_Addr                   : in  std_logic_vector(0 to 31);
Bus2IP_CS                   : in  std_logic_vector(0 to 0);
Bus2IP_RNW                   : in  std_logic;
Bus2IP_Data                   : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE                   : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE                   : in  std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE                   : in  std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data                   : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck                : out std_logic;
IP2Bus_WrAck                : out std_logic;
IP2Bus_Error                : out std_logic
);
  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
end entity user_logic;
  signal slv_reg0                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel             : std_logic_vector(0 to 3);
  signal slv_reg_read_sel             : std_logic_vector(0 to 3);
  signal slv_ip2bus_data             : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                : std_logic;
  signal slv_write_ack                : std_logic;
begin
  --USER logic implementation added here
  process( Bus2IP_Clk ) is
  begin
  if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
   if Bus2IP_Reset = '1' then
      slv_reg0 <= (others => '0');
      slv_reg1 <= (others => '0');
      slv_reg2 <= (others => '0');
      slv_reg3 <= (others => '0');
   else
      case slv_reg_write_sel is
   when "1000" =>
   LED(0 to 1) <= slv_reg0(0 to 1);
   when "0100" =>
   LED(2 to 3) <= slv_reg1(2 to 3);
   when "0010" =>
   LED(4 to 5) <= slv_reg2(4 to 5);
   when "0001" =>
   LED(6 to 7) <= slv_reg3(6 to 7);
   when others => null;
      end case;
   end if;
end if;
  end process;
end IMP;

只看该作者 · 2011-10-14 16:44

看着有点乱啊:dizzy:

关于xlinx 用户base的问题！

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