本帖最后由 GoldSunMonkey 于 2011-10-16 09:35 编辑
Definition什么是Partial Reconfiguration? PR就是当FPGA上的逻辑正在运行时，可以动态地修改其中一部分逻辑的技术，此时其他逻辑还是在正常运行。;P
Xilinx Partial Reconfiguration Page
我们为什么要使用PR技术呢？它能带来什么好处呢？总的来讲，好处有以下几点：
- 时分复用的逻辑只需要占用同一块FPGA芯片面积，这样就可以缩小FPGA设计所占的面积
- 不工作的逻辑不必加载到FPGA内部，这样可以节省功耗
- 保证修改时其他逻辑仍在正常运行不中断
What's the benefit of Partial Reconfiguration?
- If some modules are timing multiplexing, PR can help to save logic.
- Unload unused logic to save power.
- Keep other modules running smoothly while reconfiguration one partition.
Common Usage- In wired and wireless marketing, PR can be widely used to reconfigure one port's protocol (GSM/CDMA, etc) while keeping other ports uninterrupted.
- In the largest FPGAs, the default configuration time can not meet PCIe 100ms enumeration limit. PR can help to configure a compressed bit file to boot PCIe and then load real functions.
ToolsThe main tools for PR flow is done in PlanAhead, although all ISE tools might be used during the various phases of design and implementation.
Software Design FlowUG733 - Basic PlanAhead Design Flow
Example DesignTutorial: UG744 - Reconfigurable Processor Peripheral [PDF]Example Design Download
Xapp877 - Data Integrity and Security Controller for Partial Reconfiguration
Xapp883 - Fast Configuration for PCIe [PDF] Example Design Download
ReferencesAR25018 - PlanAhead Flow FAQ / Know Issues for the Early Access Partial PlanAhead Program
AR35381 - 12.1 Partial Reconfiguration - How can I perform CRC checks on my Partial Bitstream?
XCELL 73 Page 42 - FPGA Partial Reconfiguration Goes Mainstream <Flash|PDF> |
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