关于DMA的uart FIFO的疑问，请版主明示。

只看该作者 · 2011-10-31 21:31

TI的stellarisware里的udma_demo例程中，如下两个设置有些疑问，这里uart的fifo设置4_8,应该为fifo16字节大小的1/2，应该是8字节，这里为啥一直都说是4 byte。

//
// Set both the TX and RX trigger thresholds to 4.  This will be used by
// the uDMA controller to signal when more data should be transferred.  The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//
UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

//
// Configure the control parameters for the primary control structure for
// the UART RX channel.  The primary contol structure is used for the "A"
// part of the ping-pong receive.  The transfer data size is 8 bits, the
// source address does not increment since it will be reading from a
// register.  The destination address increment is byte 8-bit bytes.  The
// arbitration size is set to 4 to match the RX FIFO trigger threshold.
// The uDMA controller will use a 4 byte burst transfer if possible.  This
// will be somewhat more effecient that single byte transfers.
//
uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT,
                        UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
                        UDMA_ARB_4);