/**************************************************************************//**
* @file main.c
* @version V2.10
* $Revision: 3 $
* $Date: 14/01/28 11:44a $
* @brief M051 Series Timer Controller and Watchdog Timer Driver Sample Code
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "M051Series.h"
#define PLLCON_SETTING CLK_PLLCON_50MHz_HXT
#define PLL_CLOCK 50000000
void SYS_Init(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable External XTAL (4~24 MHz) */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
CLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
i = 22000000; // For timeout
while(i-- > 0)
{
if((CLK->CLKSTATUS & (CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk)) ==
(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk))
break;
}
/* Switch HCLK clock source to PLL */
CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL;
/* Enable IP clock */
CLK->APBCLK = CLK_APBCLK_UART0_EN_Msk;
/* Select IP clock source */
CLK->CLKSEL1 = CLK_CLKSEL1_UART_S_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
}
void UART0_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS->IPRSTC2 |= SYS_IPRSTC2_UART0_RST_Msk;
SYS->IPRSTC2 &= ~SYS_IPRSTC2_UART0_RST_Msk;
/* Configure UART0 and set UART0 Baudrate */
UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(PLL_CLOCK, 115200);
UART0->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
}
void HDIV_Init(void)
{
/* Enable Hardware Divider Clock */
CLK->AHBCLK |= CLK_AHBCLK_HDIV_EN_Msk;
}
/*---------------------------------------------------------------------------------------------------------*/
/* MAIN function */
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
/* Disable register write-protection function */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Init UART0 for printf */
UART0_Init();
/* Init Divider */
HDIV_Init();
printf("+----------------------------------------------+\n");
printf("| M05xx Divider Sample Code |\n");
printf("+----------------------------------------------+\n");
printf("\n");
printf("12341 / 123 = %d\n", HDIV_Div(12341, 123));
printf("12341 %% 123 = %d\n", HDIV_Mod(12341, 123));
HDIV->DIVIDEND = 12341;
HDIV->DIVISOR = 123;
printf("12341 / 123 = %d, remainder = %d\n", HDIV->DIVQUO, HDIV->DIVREM);
/* Lock protected registers */
SYS_LockReg();
printf("Done\n");
while(SYS->PDID);
return 0;
}
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