应用中想得到灵活的时钟，就想到altpll_reconfig。但是今天实际操作，发现配置后不能锁定。以下是配置代码。（先输出18MHZ时钟一会，然后修改成9MHZ）
module setpll(
clk,
rst_n,
busy,
reconfig,
read_param,
write_param,
data_out,
counter_type,
counter_param,
pll_areset_out,
reset
);
input clk;
input rst_n;
input busy;
output reconfig;
output read_param;
output write_param;
output [8:0] data_out;
output [3:0] counter_type;
output [2:0] counter_param;
output pll_areset_out;
output reset;
reg reconfig;
reg read_param;
reg write_param;
reg [8:0] data_out;
reg [3:0] counter_type;
reg [2:0] counter_param;
reg pll_areset_out;
reg reset;
reg [31:0] count;
reg [3:0] state;
parameter idle =4'b0000,
s0 =4'b0001,
s1 =4'b0010,
s2 =4'b0011,
s3 =4'b0100,
s4 =4'b0101,
s5 =4'b0110,
s6 =4'b0111,
s7 =4'b1000,
s8 =4'b1001,
s9 =4'b1010,
s10 =4'b1011,
s11 =4'b1100;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reconfig <=0;
read_param <=0;
write_param <=0;
data_out <=9'd0;
counter_type<=4'b0000;
counter_param<=3'b000;
pll_areset_out<=1;
reset <=1;
count <=32'd0;
state <= idle;
end
else begin
case(state)
idle: begin
reconfig <=0;
read_param <=0;
write_param <=0;
data_out <=9'd0;
counter_type<=4'b0000;
counter_param<=3'b000;
pll_areset_out<=1;
reset <=1;
count <= count +32'd1;
if(count==32'h10000000)
state <= s9;
end
s9:begin
pll_areset_out<=0;
reset <=0;
count <= count +32'd1;
if(count==32'h20000000)
state <= s0;
end
s0: begin
data_out <=9'd36;
counter_type<=4'b0100;
counter_param<=3'b000;
state <= s1;
end
s1: begin
count <= count +32'd1;
if(count==32'h21000000) begin
if(!busy) begin
write_param <=1;
state <= s2;
end
end
end
s2: begin
write_param <=0;
state <= s3;
end
s3: begin
if(!busy)
state <= s4;
end
s4: begin
data_out <=9'd36;
counter_type<=4'b0100;
counter_param<=3'b001;
state <= s5;
end
s5: begin
if(!busy) begin
write_param <=1;
state <= s6;
end
end
s6: begin
write_param <=0;
state <= s7;
end
s7: begin
if(!busy) begin
reconfig <=1;
state <= s8;
end
end
s8: begin
reconfig <=0;
if(!busy)
state <= s10;
end
s10: begin
// pll_areset_out<=1;
state <= s11;
end
s11: begin
// pll_areset_out<=0;
state <= s11;
end
default:
state <= idle;
endcase
end
end
endmodule |
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