有如下代码，功能是实现统计输入数据中1的个数，实现该功能可以有很多种方式，但是我看到一本书上用了这种方式，就是嵌套事件控制（embedded timing control），该书上举此例是想说明 static loop with embedded timing control were supported by the synthesis tool。此处的综合工具为Synopsys Design Compiler。
代码如下：module counter_1s
(
output reg [2:0] bit_count,
input clk,reset,
input [3:0] data
);
reg [2:0] count;
reg [3:0] temp;
always
begin : wrapper
@(posedge clk)
if(reset) begin count=0;bit_count=0;end
else begin :bit_counter
count=0;
temp=data;
while(temp)
@(posedge clk)
if(reset)begin
count=2'b0;
disable bit_counter;
end
else begin
count=count+temp[0];
temp=temp>>1;
end
@(posedge clk)
if(reset) begin
count=0;
disable bit_counter;
end
else bit_count=count;
end
end
endmodule
而编译出错：Error (10856): Verilog HDL error at counter_1s.v(19): multiple event control statements not supported for synthesis
这是什么原因？我使用的Quartus II v10.1版本，是quartus的综合工具不支持么？ |
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