| UCB0CTL1 |= UCSWRST; // Enable SW reset UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
 UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
 UCB0BR0 = 20; // fSCL = SMCLK/20 = 400kHz
 UCB0BR1 = 0;
 
 UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
 |