Important notes STM32F103xx
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Appendix A Important notes
The notes listed below apply to STM32F103xx devices Revision Z. For more details on how
to identify the device Revision, please refer to section 20.6.1 MCU device ID code in the
STM32F10xxx reference manual.
A.1 PD0 and PD1 use in output mode
The use of PD0 and PD1 in output mode is limited as in this mode, PD0 and PD1 can only
be used at 50 MHz.
A.2 ADC auto-injection channel
When the ADC clock prescaler ranges from 4 to 8, a delay of 1 ADC clock period is
automatically inserted when switching from regular to injected conversion (and conversely,
from injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock
periods.
A.3 ADC combined injected simultaneous + interleaved
When the ADC clock prescaler is set to 4, the interleaved mode does not recover with
evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6
ADC clock periods, instead of 7 clock periods followed by 7 clock periods.
A.4 Voltage glitch on ADC input 0
A low-amplitude voltage glitch can be generated on ADC input 0, when the ADC is
converting with injection trigger, in very specific cases.
It is generated by internal coupling and synchronized to the beginning and the end of the
injection sequence, whatever the channel(s) to be converted.
It has an amplitude of less than 150 mV and a typical duration of 10 ns (measured with the
I/O left unconnected). This has no influence on the digital output signals or the digital inputs,
providing that they are driven with a reasonably low impedance.
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