工程文件
//Verilog规定:以module开头,以endmodule结尾
//module后面接模块名(必须和文件名一致)
//模块名后面是括号,括号里面是端口定义,外面是分号
module and_gate(a, b, s);
input a; //输入信号a
input b; //输入信号b
output s; //输出信号c
//数据流建模(二输入与门)
assign s = a & b;
endmodule
测试文件:
`timescale 1ns/1ps
module and_gate_tb;
reg a;
reg b;
wire s;
and_gate and_gate(
.a(a),
.b(b),
.s(s)
);
//初始化
initial
begin
a = 0; b = 0;
#100 a = 0; b = 1; //#代表延时,100代表数值大小,单位ns
#100 a = 1; b = 0;
#100 a = 1; b = 1;
#100 $stop; //停机
end
endmodule
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