大家好，小弟刚在学习状态机的VHDL建模，看到一例子，状态转移图如下：
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下面VHDL的描述：
type state is (step1, step2, step3);
signal current_state, next_state : state;
STATE_REG : process(clk) is
begin
if rising_edge(clk) then
if reset = '1' then
current_state <= step1;
else
current_state <= next_state;
end if;
end if;
end process STATE_REG;
NEXT_STATE_REG : process (start) is
begin
case current_state is
when step1 =>
if start = '0' then
next_state <= step1;
else
next_state <= step2;
end if;
when step2 =>
next_state <= step3;
when step3 =>
next_State <= step1;
end case;
end process NEXT_STATE_REG;
对这个例子有一个疑问，为什么进程NEXT_STATE_REG 需要加入start敏感信号量，我记得进程是只有敏感信号量变化才会启动执行的，但事实上，在状态2到状态3的转化，并不需要敏感信号量start变化，这是为什么呢？ |
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