本帖最后由 2287312853 于 2020-2-5 10:19 编辑
DSP是TMS320F28335,SYSTEMCLK=15OMHz
CPLD是EPM1270TI4415，CLK=10MHz- SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; //开启XINTF时钟信号
- XintfRegs.XINTCNF2.bit.XTIMCLK = 1; //基准时钟XTIMCLK = 1/2 SYSCLKOUT
- XintfRegs.XINTCNF2.bit.WRBUFF = 0; //无写缓冲寄存器
- XintfRegs.XINTCNF2.bit.CLKOFF = 0; //开启XCLKOUT
- XintfRegs.XINTCNF2.bit.CLKMODE = 0; //XCLKOUT=XTIMCLK
- XintfRegs.XTIMING0.bit.XWRLEAD = 3; //区域0写建立时间为11b，周期数为6
- XintfRegs.XTIMING0.bit.XWRACTIVE = 7; //有效时间为111b，周期数为14
- XintfRegs.XTIMING0.bit.XWRTRAIL = 3; //跟踪时间为11b，周期数为6
- // Zone read timing
- XintfRegs.XTIMING0.bit.XRDLEAD = 3; //区域0读建立时间为11b，周期数为6
- XintfRegs.XTIMING0.bit.XRDACTIVE = 7; //有效时间为111b，周期数为14
- XintfRegs.XTIMING0.bit.XRDTRAIL = 3; //跟踪时间为11b，周期数为6
- // double all Zone read/write lead/active/trail timing
- XintfRegs.XTIMING0.bit.X2TIMING = 0; //比值1:1
- // Zone will sample XREADY signal
- XintfRegs.XTIMING0.bit.USEREADY = 1; //XREADY信号采样
- XintfRegs.XTIMING0.bit.READYMODE = 1; //异步采样
- XintfRegs.XTIMING0.bit.XSIZE = 3; //数据总线宽度，16位
这个是程序，起始地址为0x4000h
00h～3Fh，ZONE0映射到CPLD
CPLD在硬件上只有DSP给的XA0~XA12共13根地址线，进行译码等操作
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