/**************************************************************************//**
* @file main.c
* @version V1.00
* $Revision: 4 $
* $Date: 15/05/22 2:05p $
* @brief Generate different frequency(Tenor C Do ~ Si) waveform by PWM.
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "M051Series.h"
/*---------------------------------------------------------------------------------------------------------*/
/* Macro, type and constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PLLCON_SETTING CLK_PLLCON_50MHz_HXT
#define PLL_CLOCK 50000000
/*---------------------------------------------------------------------------------------------------------*/
/* Global variables */
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);
/* Enable PLL and Set PLL frequency */
CLK_SetCoreClock(PLLCON_SETTING);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable PWM module clock */
CLK_EnableModuleClock(PWM01_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Select PWM module clock source */
CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0);
/* Reset PWMA channel0~channel3 */
SYS_ResetModule(PWM03_RST);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);
SYS->P3_MFP |= SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P4 multi-function pins for PWMA Channel0 */
// SYS->P4_MFP &= ~(SYS_MFP_P40_Msk|SYS_MFP_P41_Msk);
// SYS->P4_MFP |= (SYS_MFP_P40_PWM0|SYS_MFP_P41_PWM1);
SYS->P4_MFP &= ~(SYS_MFP_P41_Msk);
SYS->P4_MFP |= (SYS_MFP_P41_PWM1);
}
void UART0_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint8_t i=100;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
// PWM_EnableOutput(PWMA, 0x1|0x2);
PWM_EnableOutput(PWMA, 0x2);
// PWM_ConfigOutputChannel(PWMA, PWM_CH0, 1000, i);
PWM_ConfigOutputChannel(PWMA, PWM_CH1, 1000, 100-i);
// PWM_Start(PWMA, 0x1|0x2);
PWM_Start(PWMA, 0x2);
while(1)
{
while(i>0)
{
i=i-5;
// PWM_ConfigOutputChannel(PWMA, PWM_CH0, 1000, i);
PWM_ConfigOutputChannel(PWMA, PWM_CH1, 1000, 100-i);
CLK_SysTickDelay(10000);
}
while(i<100)
{
i=i+5;
// PWM_ConfigOutputChannel(PWMA, PWM_CH0, 1000, i);
PWM_ConfigOutputChannel(PWMA, PWM_CH1, 1000, 100-i);
CLK_SysTickDelay(10000);
}
}
}
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看了一遍代码，没发现大毛病，可能是因为0和1是一对，如果使用1，应该配置0.我的代码是先配置的0，测试的，OK。然后添加了1测试也是OK