typedef struct
{
/**
* [url=home.php?mod=space&uid=176933]@VAR[/url] GPIO_T::PMD
* Offset: 0x00/0x40/0x80/0xC0/0x100 Port 0-4 I/O Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|PMDn |Determine each I/O mode of Px.n pins.
* | | |00 = Px.n is in Input mode.
* | | |01 = Px.n is in Push-pull Output mode.
* | | |10 = Px.n is in Open-drain Output mode.
* | | |11 = Px.n is in Quasi-bidirectional mode.
* | | |Note1: x = 0~4, n = 0~7.
* | | |Note2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).
* | | |Note3: The initial value of this field is defined by CIOINI (CONFIG[10]) (only for M05xxDN/DE).
* | | |If CIOINI is set to 1, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
* | | |If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input tri-state mode after chip powered on.
* @var GPIO_T::OFFD
* Offset: 0x04/0x44/0x84/0xC4/0x104 Port 0-4 Digital Input Path Disable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |OFFD |Port 0-4 Pin [n] Digital Input Path Disable Control
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
* | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
* | | |0 = Px.n digital input path Enabled.
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
* | | |Note: x = 0~4, n = 0~7.
* @var GPIO_T::DOUT
* Offset: 0x8/0x48/0x88/0xC8/0x108 Port 0-4 Data Output Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DOUT[n] |Port 0-4 Pin [n] Output Value
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
* | | |Note: x = 0~4, n = 0~7.
* @var GPIO_T::DMASK
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C Port 0-4 Data Output Write Mask
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DMASK[n] |Port 0-4 Pin [n] Data Output Write Mask
* | | |These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected.
* | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding Px_DOUT[n] bit can be updated.
* | | |1 = Corresponding Px_DOUT[n] bit protected.
* | | |Note1: x = 0~4, n = 0~7.
* | | |Note2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit.
* @var GPIO_T::PIN
* Offset: 0x10/0x50/0x90/0xD0/0x110 Port 0-4 Pin Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PIN[n] |Port 0-4 Pin [n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
* | | |Note: x = 0~4, n = 0~7.
* @var GPIO_T::DBEN
* Offset: 0x14/0x54/0x94/0xD4/0x114 Port 0-4 De-bounce Enable
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DBEN[n] |Port 0-4 Pin [n] Input Signal De-bounce Enable Control
* | | |DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
* | | |The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].
* | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note1: x = 0~4, n = 0~7.
* | | |Note2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function.
* @var GPIO_T::IMD
* Offset: 0x18/0x58/0x98/0xD8/0x118 Port 0-4 Interrupt Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IMD[n] |Port 0-4 Pin [n] Edge or Level Detection Interrupt Mode Control
* | | |IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger.
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers Px_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: x = 0~4, n = 0~7.
* @var GPIO_T::IEN
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C Port 0-4 Interrupt Enable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:16] |IR_EN[n] |Port 0-4 Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
* | | |IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the IR_EN[n] bit to 1 :
* | | |If the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
* | | |If the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
* | | |0 = Px.n level high or low to high interrupt Disabled.
* | | |1 = Px.n level high or low to high interrupt Enabled.
* | | |Note: x = 0~4, n = 0~7.
* |[7:0] |IF_EN[n] |Port 0-4 Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
* | | |IF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the IF_EN[n] bit to 1 :
* | | |If the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
* | | |If the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
* | | |0 = Px.n level low or high to low interrupt Disabled.
* | | |1 = Px.n level low or high to low interrupt Enabled.
* | | |Note: x = 0~4, n = 0~7.
* @var GPIO_T::ISRC
* Offset: 0x20/0x60/0xA0/0xE0/0x120 Port 0-4 Interrupt Trigger Source
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |ISRC[n] |Port 0-4 Pin [n] Interrupt Source Flag
* | | |Write :
* | | |0 = No action.
* | | |1 = Clear the corresponding pending interrupt.
* | | |Read :
* | | |0 = No interrupt at Px.n.
* | | |1 = Px.n generates an interrupt.
* | | |Note: x = 0~4, n = 0~7.
*/
__IO uint32_t PMD; /* Offset: 0x00/0x40/0x80/0xC0/0x100 Port 0-4 I/O Mode Control */
__IO uint32_t OFFD; /* Offset: 0x04/0x44/0x84/0xC4/0x104 Port 0-4 Digital Input Path Disable Control */
__IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108 Port 0-4 Data Output Value */
__IO uint32_t DMASK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C Port 0-4 Data Output Write Mask */
__IO uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110 Port 0-4 Pin Value */
__IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114 Port 0-4 De-bounce Enable */
__IO uint32_t IMD; /* Offset: 0x18/0x58/0x98/0xD8/0x118 Port 0-4 Interrupt Mode Control */
__IO uint32_t IEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C Port 0-4 Interrupt Enable Control */
__IO uint32_t ISRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120 Port 0-4 Interrupt Trigger Source */
} GPIO_T;
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