PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral
interrupts. PIR1 REGISTER
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF SSPIF:Synchronous Serial Port Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software
before returning from the interrupt Service Routine. The condition that will
set this are:
SPI-A transmission/reception has taken,place.
I2C Slave - A transmission/reception has taken place.
I2C Master
0 = No SSP interrupt condition has occurred.
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