External Bus Interface (EBI)
6.21.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports two chip selects that can connect two external devices with different
timing setting requirements.
6.21.2 Features
Supports up to two memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports address bus and data bus separate mode
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