<font size="2">#include <stdio.h>
#include "NuMicro.h"
/*---------------------------------------------------------------------------------------------------------*/
/* Macro, type and constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------------------*/
/* Global variables */
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Set PF multi-function pins for XT1_OUT(PF.2) and XT1_IN(PF.3) */
SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SYS_GPF_MFPL_PF2MFP_Msk)) | XT1_OUT_PF2;
SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SYS_GPF_MFPL_PF3MFP_Msk)) | XT1_IN_PF3;
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184 MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Enable PLL */
CLK->PLLCTL = CLK_PLLCTL_128MHz_HIRC;
/* Waiting for PLL stable */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Select HCLK clock source as PLL and HCLK source divider as 2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Enable EPWM1 module clock */
CLK_EnableModuleClock(EPWM1_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* EPWM clock frequency configuration */
/*---------------------------------------------------------------------------------------------------------*/
CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
/* Reset EPWM1 module */
SYS_ResetModule(EPWM1_RST);
/* Update System Core Clock */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFPH = (SYS->GPB_MFPH & (~(UART0_RXD_PB12_Msk | UART0_TXD_PB13_Msk))) | UART0_RXD_PB12 | UART0_TXD_PB13;
/* Set PC multi-function pins for EPWM1 Channel 0~1 */
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC5MFP_Msk)) | EPWM1_CH0_PC5;
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC4MFP_Msk)) | EPWM1_CH1_PC4;
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
/* Init System, IP clock and multi-function I/O
In the end of SYS_Init() will issue SYS_LockReg()
to lock protected register. If user want to write
protected register, please issue SYS_UnlockReg()
to unlock protected register if necessary */
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART to 115200-8n1 for print message */
UART0_Init();
printf("\n\nCPU [url=home.php?mod=space&uid=72445]@[/url] %dHz(PLL@ %dHz)\n", SystemCoreClock, PllClock);
printf("+-----------------------------------------------------------+\n");
printf("| EPWM Driver |\n");
printf("| |\n");
printf("+-----------------------------------------------------------+\n");
printf(" This code will output waveform with EPWM1 channel 0~1.\n");
printf(" I/O configuration:\n");
printf(" EPWM1 channel 0: 100 kHz, duty 40%%.\n");
printf(" EPWM1 channel 1: 100 kHz, duty 60%%.\n");
printf(" Waveform output pin: EPWM1_CH0(D3), EPWM1_CH1(D2),\n");
/* Set EPWM mode as complementary mode */
EPWM_ENABLE_COMPLEMENTARY_MODE(EPWM1);
/* EPWM1 channel 0~1 frequency and duty configuration are as follows */
EPWM_ConfigOutputChannel(EPWM1, 0, 100000, 40);
/* Enable output of EPWM1 channel 0~1 */
EPWM_EnableOutput(EPWM1, 0x3F);
/* Start EPWM1 counter */
EPWM_Start(EPWM1, 0x3F);
printf("Press any key to stop.\n");
getchar();
/* Start EPWM1 counter */
EPWM_ForceStop(EPWM1, 0x3F);
printf("Done.");
while(1);
}</font>
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