code uchar TX_ADDRESS[5]= {0x34,0x43,0x10,0x10,0x01}; //±¾µØµØÖ·
code uchar RX_ADDRESS[5]= {0x34,0x43,0x10,0x10,0x01}; //½ÓÊÕµØÖ·
。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。
//****************************************************************************************
/*NRF24L01³õʼ»¯
//***************************************************************************************/
void init_NRF24L01(void)
{
inerDelay_us(100);
CE=0; // chip enable
CSN=1; // Spi disable
SCK=0; // Spi clock line init high
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // д±¾µØµØÖ·
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); // д½ÓÊն˵ØÖ·
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // ƵµÀ0×Ô¶¯ ACKÓ¦´ðÔÊÐí
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // ÔÊÐí½ÓÊÕµØÖ·Ö»ÓÐƵµÀ0£¬Èç¹ûÐèÒª¶àƵµÀ¿ÉÒԲο¼Page21
SPI_RW_Reg(WRITE_REG + RF_CH, 0); // ÉèÖÃÐŵÀ¹¤×÷Ϊ2.4GHZ£¬ÊÕ·¢±ØÐëÒ»ÖÂ
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //ÉèÖýÓÊÕÊý¾Ý³¤¶È£¬±¾´ÎÉèÖÃΪ32×Ö½Ú
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); //ÉèÖ÷¢ÉäËÙÂÊΪ2MHZ£¬·¢É书ÂÊΪ×î´óÖµ0dB
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQÊÕ·¢Íê³ÉÖжÏÏìÓ¦£¬16λCRC£¬Ö÷·¢ËÍ
}
xdata uchar TxBuf[32]=
{
0x01,0x02,0x03,0x4,0x05,0x06,0x07,0x08,
0x09,0x10,0x11,0x12,0x13,0x14,0x15,0x16,
0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24,
0x25,0x26,0x27,0x28,0x29,0x30,0x31,0x32,
}; // |