/**************************************************************************//**
* [url=home.php?mod=space&uid=288409]@file[/url] main.c
* [url=home.php?mod=space&uid=895143]@version[/url] V3.00
* $Revision: 2 $
* $Date: 16/10/25 4:29p $
* @brief
* Change duty cycle of output waveform by configured period.
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NUC029xGE.h"
/*---------------------------------------------------------------------------------------------------------*/
/* Macro, type and constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PLL_CLOCK 144000000
/*---------------------------------------------------------------------------------------------------------*/
/* Global variables */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t CalNewDutyCMR(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32DutyCycle, uint32_t u32CycleResolution);
/**
* [url=home.php?mod=space&uid=247401]@brief[/url] PWM0 IRQ Handler
*
* @param None
*
* [url=home.php?mod=space&uid=266161]@return[/url] None
*
* [url=home.php?mod=space&uid=1543424]@Details[/url] ISR to handle PWM0 interrupt event
*/
void PWM0_IRQHandler(void)
{
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
// CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Enable PWM0 module clock */
CLK_EnableModuleClock(PWM0_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* PWM clock frequency configuration */
/*---------------------------------------------------------------------------------------------------------*/
/* Select HCLK clock source as PLL and and HCLK clock divider as 2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
/* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */
/* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */
CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL1_PWM0SEL_PCLK0, NULL);
/* case 2.PWM clock frequency is set double to HCLK: select PWM module clock source as PLL */
//CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL1_PWM0SEL_PLL, NULL);
/*---------------------------------------------------------------------------------------------------------*/
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* Reset PWM0 module */
SYS_ResetModule(PWM0_RST);
/* Update System Core Clock */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set multi-function pins for UART0 RXD and TXD */
SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk);
SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_UART0_RXD | SYS_GPA_MFPL_PA2MFP_UART0_TXD);
/* Set PC multi-function pins for PWM0 Channel0~3 */
SYS->GPC_MFPL = (SYS->GPC_MFPL & ~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk)) | \
(SYS_GPC_MFPL_PC0MFP_PWM0_CH0 | SYS_GPC_MFPL_PC1MFP_PWM0_CH1 | SYS_GPC_MFPL_PC2MFP_PWM0_CH2 | SYS_GPC_MFPL_PC3MFP_PWM0_CH3);
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART module */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
/**
* @brief Calculate the comparator value of new duty by configured period
*
* @param pwm The pointer of the specified PWM module
*
* @param u32ChannelNum PWM channel number. Valid values are between 0~5
*
* @param u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ u32CycleResolution.
* If u32CycleResolution is 100, and u32DutyCycle is 10 means 10%, 20 means 20% ...
*
* @param u32CycleResolution Target generator duty cycle resolution. The value in general is 100.
*
* @return The compatator value by new duty cycle
*/
uint32_t CalNewDutyCMR(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32DutyCycle, uint32_t u32CycleResolution)
{
return (u32DutyCycle * (PWM_GET_CNR(pwm, u32ChannelNum) + 1) / u32CycleResolution);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint8_t u8Option;
uint32_t u32NewDutyCycle = 0, u32NewCMR = 0;
/* Init System, IP clock and multi-function I/O
In the end of SYS_Init() will issue SYS_LockReg()
to lock protected register. If user want to write
protected register, please issue SYS_UnlockReg()
to unlock protected register if necessary */
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART to 115200-8n1 for print message */
UART0_Init();
printf("\n\nCPU [url=home.php?mod=space&uid=72445]@[/url] %dHz(PLL@ %dHz)\n", SystemCoreClock, PllClock);
printf("PWM0 clock is from %s\n", (CLK->CLKSEL1 & CLK_CLKSEL1_PWM0SEL_Msk) ? "CPU" : "PLL");
printf("+-----------------------------------------------------------------------------------+\n");
printf("| PWM Driver Sample Code |\n");
printf("| |\n");
printf("+-----------------------------------------------------------------------------------+\n");
printf(" This sample code will use PWM0 channel 0 to output waveform, and switch duty cycle.\n");
printf(" I/O configuration:\n");
printf(" waveform output pin: PWM0 channel 0(PC.0)\n");
printf("\nOutput waveform is 1800Hz and it's duty is 50%.\n");
/*
Configure PWM0 channel 0 init period and duty(up counter type).
Period is PLL / (prescaler * (CNR + 1))
Duty ratio = (CMR) / (CNR + 1)
Period = 72 MHz / (2 * (19 + 1)) = 1800000 Hz
Duty ratio = (100) / (19 + 1) = 50%
*/
/* PWM0 channel 0 frequency is 1800Hz, duty 50%, */
PWM_ConfigOutputChannel(PWM0, 0, 1800, 50);
/* Enable output of PWM0 channel 0 */
PWM_EnableOutput(PWM0, PWM_CH_0_MASK);
/* Start PWM counter */
PWM_Start(PWM0, PWM_CH_0_MASK);
while(1)
{
printf("\nSelect new duty: \n");
printf("[1] 100%% \n");
printf("[2] 75%% \n");
printf("[3] 25%% \n");
printf("[4] 0%% \n");
printf("[Other] Exit \n");
u8Option = getchar();
if(u8Option == '1')
{
u32NewDutyCycle = 100;
}
else if(u8Option == '2')
{
u32NewDutyCycle = 75;
}
else if(u8Option == '3')
{
u32NewDutyCycle = 25;
}
else if(u8Option == '4')
{
u32NewDutyCycle = 0;
}
else
{
printf("Exit\n");
break;
}
/* Get new comparator value by call CalNewDutyCMR() */
u32NewCMR = CalNewDutyCMR(PWM0, 0, u32NewDutyCycle, 100);
/* Set new comparator value to register */
PWM_SET_CMR(PWM0, 0, u32NewCMR);
}
/* Stop PWM counter */
PWM_Stop(PWM0, PWM_CH_0_MASK);
/* Disable output of PWM0 channel 0 */
PWM_DisableOutput(PWM0, PWM_CH_0_MASK);
while(1);
}
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