////////////////////////////////////////////////////////////////////////////////
/// @brief RCC Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR; ///< Control Register offset: 0x00
__IO u32 CFGR; ///< Configuration Register offset: 0x04
__IO u32 CIR; ///< Clock Interrupt Register offset: 0x08
__IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x0C
__IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x10
__IO u32 AHBENR; ///< Advanced High Performance Bus Enable Register offset: 0x14
__IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x18
__IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x1C
__IO u32 RESERVED0; ///< Reserved offset: 0x20
__IO u32 CSR; ///< Control Status Register offset: 0x24
__IO u32 AHBRSTR; ///< Advanced High Performance Bus Reset Register offset: 0x28
__IO u32 RESERVED2; ///< Reserved offset: 0x2C
__IO u32 RESERVED3; ///< Reserved offset: 0x30
__IO u32 RESERVED4; ///< Reserved offset: 0x34
__IO u32 RESERVED5; ///< Reserved offset: 0x38
__IO u32 RESERVED6; ///< Reserved offset: 0x3C
__IO u32 SYSCFG; ///< System Configuration Register offset: 0x40
} RCC_TypeDef;
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