A-R-M seems not mention anything about this data cache flush of changing table entry.
From A-R-M of ARMv8-Cortex-A (DDI 0487D.a), the G.5.9 TLB maintenance requirements,
we do not see any hint about the necessary to flush data cache of table entry.
The only one example for a uniprocessor system in G.5.9.1, there is no data cache flush operation.
Therefore, in a uniprocessor system, an example instruction sequence for writing a translation table entry, covering
changes to the instruction or data mappings is:
STR rx, [Translation table entry] ; write new entry to the translation table
DSB ; ensures visibility of the new entry
Invalidate TLB entry by VA (and ASID if non-global) [page address]
Invalidate BTC
DSB ; ensure completion of the Invalidate TLB instruction
ISB ; ensure table changes visible to instruction fetch
For SMP system, It neither not find anything about necessary of data cache flush operation. |
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