附上我的程序
CLA初始化:
void InitCLA_Driver(void)
{
// Copy the program and constants from FLASH to RAM before configuring
// the CLA
//
#if defined(_FLASH)
memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,
(uint32_t)&Cla1ProgLoadSize );
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
(uint32_t)&Cla1ConstLoadSize );
#endif //defined(_FLASH)
EALLOW;
// CLA Program will reside in RAMLS0 and data in RAMLS1, RAMLS2
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0U;
// Select CLA as the master of RAMLS0, RAMSL1, RAMLS2
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1U;
//
// Suppressing #770-D conversion from pointer to smaller integer
// The CLA address range is 16 bits so the addresses passed to the MVECT
// registers will be in the lower 64KW address space. Turn the warning
// back on after the MVECTs are assigned addresses
//
#pragma diag_suppress=770
//
// Assign the task vectors and set the triggers for task 1 and 7
//
Cla1Regs.MVECT1 = (uint16_t)&Cla1Task1;
/*Set actions*/
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
/*Set INT*/
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1rd event
EPwm4Regs.ETCLR.bit.INT = 1;
EPwm4Re4 should run freely in emulation mode
//
//EPwm4Regs.TBCTL.bit.FREE_SOFT = 2U;
EDIS;
}
CLA中断:
{
__attribute__((interrupt)) void cla1_task1_isr(void){
EALLOW;
PieCtrlRegs.PIEACK.bit.ACK11 = 1U; // Acknowledge the end-of-task interrupt for task 1
EPwm4Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
EDIS;
}