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Task3 Interrupt via Register Access If you want to try the interrupt via register access, you can use the following code to realize the same function. In CCS project, click New CCS project, and select the MSP432 device family and MSP432P401R, click Finish.
Add the following code to the main.c, the final main.c looks like this #include "msp.h"/** * main.c */void main(void){ WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // stop watchdog timer // Configuring P1.0 as output and P1.1 (switch) as input with pull-up // resistor. Rest of pins are configured as output low. // Notice intentional '=' assignment since all P1 pins are being // deliberately configured P1->DIR = ~(uint8_t) BIT1; P1->OUT = BIT1; P1->REN = BIT1; // Enable pull-up resistor (P1.1 output high) P1->SEL0 = 0; P1->SEL1 = 0; P1->IES = BIT1; // Interrupt on high-to-low transition P1->IFG = 0; // Clear all P1 interrupt flags P1->IE = BIT1; // Enable interrupt for P1.1 // Enable Port 1 interrupt on the NVIC NVIC->ISER[1] = 1 << ((PORT1_IRQn) & 31); // Terminate all remaining pins on the device P2->DIR |= 0xFF; P2->OUT = 0; P3->DIR |= 0xFF; P3->OUT = 0; P4->DIR |= 0xFF; P4->OUT = 0; P5->DIR |= 0xFF; P5->OUT = 0; P6->DIR |= 0xFF; P6->OUT = 0; P7->DIR |= 0xFF; P7->OUT = 0; P8->DIR |= 0xFF; P8->OUT = 0; P9->DIR |= 0xFF; P9->OUT = 0; P10->DIR |= 0xFF; P10->OUT = 0; // Enable global interrupt __enable_irq();}/* Port1 ISR */void PORT1_IRQHandler(void){ volatile uint32_t i; // Toggling the output on the LED if(P1->IFG & BIT1) P1->OUT ^= BIT0; // Delay for switch debounce for(i = 0; i < 10000; i++) P1->IFG &= ~BIT1;}Task4 Systick InterruptIn this task, we will bink the LED periodically using the SysTick module. If we want to use the new created project in Task3, when we add the include for the driverlib
/* DriverLib Includes */#include <ti/devices/msp432p4xx/driverlib/driverlib.h>When you compile the project, it will show driverlib.h not found. The reason is that the SDK include path is not setup in the CCS Cloud. You can right click the project and select the project properties->ARM Compiler
If you check the previous sample code from Lab1: “gpio_toggle_output”, you will see the complete setup of the SDK path.
If you want to use the DriverLib in the CCS Cloud, you should change the code based on the previous “gpio_toggle_output” sample not the new project. Due to the limitation of the CCS Cloud, you cannot change the include path manually. Another option is to use the CCS local version. You can add the path manually. But, TI recommends to import the sample code directly to save the time for path configuration. You can duplicate the sample project “gpio_toggle_output”, then rename the project and the project file name.
Add the following code to the main.c /* DriverLib Includes */#include <ti/devices/msp432p4xx/driverlib/driverlib.h>/* Standard Includes */#include <stdint.h>#include <stdbool.h>int main(void){ volatile uint32_t ii; /* Halting the Watchdog */ MAP_WDT_A_holdTimer(); /* Configuring P1.0 as LED */ MAP_GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0); /* Initializing MCLK to REFO */ MAP_CS_initClockSignal(CS_MCLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); /* Configuring SysTick to trigger at 16000. */ MAP_SysTick_enableModule(); MAP_SysTick_setPeriod(3000000);//16000 MAP_SysTick_enableInterrupt(); /* Enabling MASTER interrupts */ MAP_Interrupt_enableMaster(); while (1) { }}/* SysTick ISR */void SysTick_Handler(void){ MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P1, GPIO_PIN0);}In the previous code, we first configure P1.1 as input for switch and P1.0 as LED, then Initializing MCLK to REFO and configure the SysTick. You can run the previous code and the LED in the board will blink based on the frequency setup. Comparing with the LED blinking in Lab1, this code utilizes the timer interrupt to toggle the LED without blocking the main function, i.e., empty in the while loop. MSP432 Clock system and SysTickClock system (CS) is the key to any digital system. The MSP432 contains multiple clock sources. As shown in the MSP432 datasheet Clock System part, the CS contains the sources of the various clocks in the device. It also controls the mapping between the sources and the different clocks in the device. The MSP432 clock module can be configured to operate without any external components, with up to two external crystals, or with resonators, or with an external resistor under full software control. As shown in the MSP432 Technical Reference Manual (pdf)Chapter6 (page 378), The clock system module includes the following clock resources: - LFXTCLK: Low-frequency oscillator (LFXT) that can be used either with low-frequency 32768-Hz watch crystals, standard crystals, resonators, or external clock sources in the 32-kHz or below range. When in bypass mode, LFXTCLK can be driven with an external square wave signal in the 32-kHz or below range.
- HFXTCLK: High-frequency oscillator (HFXT) that can be used with standard crystals or resonators in the 1-MHz to 48-MHz range. When in bypass mode, HFXTCLK can be driven with an external square wave signal.
- DCOCLK: Internal digitally controlled oscillator (DCO) with programmable frequencies and 3-MHz frequency by default
- VLOCLK: Internal very-low-power low-frequency oscillator (VLO) with 9.4-kHz typical frequency
- REFOCLK : Internal, low-power low-frequency oscillator (REFO) with selectable 32.768-kHz or 128kHz typical frequencies
- MODCLK: Internal low-power oscillator with 25-MHz typical frequency
- SYSOSC: Internal oscillator with 5-MHz typical frequency
The following figure shows the module for LFXTCLK, HFXTCLK, and DCOCLK.
LFXTCLK and HFXTCLK are usually connect to external crystals. If you check the schematic of the MSP432 launchpad (page36 of the MSP432 launchpad user guide), you will see crystal Q1 (2pin 32.768KHz and Q2 (4pin 48MHz).  The 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low power modes to be used. The 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. The MSP432P401R device has several internal clocks that can be sourced from many clock sources. Most peripherals on the device can select which of the internal clocks to use to operate at the desired speed.
In page14 of the MSP432 launchpad user guide
There are five system clocks inside the MSP432 to drive different module. The default configuration is shown
The definition of these five system clocks can be referred from • ACLK: Auxiliary clock. ACLK is software selectable as LFXTCLK, VLOCLK, or REFOCLK. ACLK can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. ACLK is software selectable by individual peripheral modules. ACLK is restricted to maximum frequency of operation of 128 kHz. • MCLK: Master clock. MCLK is software selectable as LFXTCLK, VLOCLK, REFOCLK, DCOCLK, MODCLK, or HFXTCLK. MCLK can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. MCLK is used by the CPU and peripheral module interfaces, as well as, used directly by some peripheral modules. • HSMCLK: Subsystem master clock. HSMCLK is software selectable as LFXTCLK, VLOCLK, REFOCLK, DCOCLK, MODCLK, HFXTCLK. HSMCLK can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. HSMCLK is software selectable by individual peripheral modules. • SMCLK: Low-speed subsystem master clock. SMCLK uses the HSMCLK clock resource selection for its clock resource. SMCLK can be divided independently from HSMCLK by 1, 2, 4, 8, 16, 32, 64, or 128. SMCLK is limited in frequency to half of the rated maximum frequency of HSMCLK. SMCLK is software selectable by individual peripheral modules. • BCLK: Low-speed backup domain clock. BCLK is software selectable as LFXTCLK and REFOCLK and is used primarily in the backup domain. BCLK is restricted to a maximum frequency of 32.768 kHz. In page 379 of MSP432 Technical Reference Manual (pdf)
In the previous sample code, we use MAP_CS_initClockSignal(CS_MCLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1) to init MCLK from REFOCLK. The function definition can be referred from driverlib guide
The REFOCLK is configurable for either 32KHz (default) or 128KHz. Thus, the previous code set MCLK=32KHz (CS_CLOCK_DIVIDER_1=1). Then, we configure SysTick to trigger at 16000. The SysTick is a basic module inside all ARM Cortex-M processors. The Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, and it is typically deployed either for operating system related purposes or as a general-purpose alarm mechanism. Part 6.2.4 of the MSP432 datasheet.
A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control State register (ICSR). In an OS environment, the processor can use this exception as system tick. In page 66 of MSP432 Technical Reference Manual (pdf)
The SysTick driverlib API can be access: [link]. It has the following functions
In the previous sample code, we first enableModule, setPeriod=16000, then enableInterrupt. The period is the number of clock ticks in each period of the SysTick counter and must be between 1 and 16,777,216. Since our MCLK=32KHz, then the SysTick interrupt period = 32KHz/16000=2Hz (0.5s period).
We also need to add the SysTick_Handler to toggle the LED for every SysTick interrupt. That’s why the LED blinks every 0.5s. Questions- If you comment the following code: MAP_CS_initClockSignal(CS_MCLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1), what kind of period value you need to set for SysTick in order to get the 1Hz LED toggle frequency? Why?
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