不好意思剛接觸新唐的板子目前想要測試SPI_SLAVE
使用的是官方提供的程式測試
C:\Nuvoton\BSP Library\M051SeriesBSP_CMSIS_Rev3.01.001\SampleCode\RegBased\SPI_SlaveFifoMode
想問的是顯示的方式是用PRINTF
可是我在debug下
debug(printf)Viewer:沒有顯示東西
[IMG] [/ IMG]
不知道我的測試方式是對不對?
我目前是開啟調試後,按下RUN,然後SPI_MASTER端傳送資料過來
新唐的SPI收到資料後,應該就會PRINT到視窗中./
/**************************************************************************//**
* @file main.c
* @version V3.0
* $Revision: 6 $
* $Date: 15/05/22 3:05p $
* @brief Configure SPI0 as Slave mode and demonstrate how to communicate
* with an off-chip SPI Master device with FIFO mode. This sample
* code needs to work with SPI_MasterFifoMode sample code.
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "M051Series.h"
#include <gpio.h>
#define TEST_COUNT 16
uint32_t g_au32SourceData[TEST_COUNT];
uint32_t g_au32DestinationData[TEST_COUNT];
volatile uint32_t g_u32TxDataCount;
volatile uint32_t g_u32RxDataCount;
/* Function prototype declaration */
void SYS_Init(void);
void UART0_Init(void);
void SPI_Init(void);
/* ------------- */
/* Main function */
/* ------------- */
int main(void)
{
GPIO_SetMode(P2,BIT7, GPIO_PMD_OUTPUT);
volatile uint32_t u32TxDataCount, u32RxDataCount;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O. */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/* Init SPI */
SPI_Init();
printf("\n\n");
printf("+----------------------------------------------------------------------+\n");
printf("| SPI Slave Mode Sample Code (M05xxDN/DE only) |\n");
printf("+----------------------------------------------------------------------+\n");
printf("\n");
printf("Configure SPI0 as a slave.\n");
printf("Bit length of a transaction: 32\n");
printf("The I/O connection for SPI0:\n");
printf(" SPISS0(P1.4)\n SPICLK0(P1.7)\n");
printf(" MISO_0(P1.6)\n MOSI_0(P1.5)\n\n");
printf("SPI controller will enable FIFO mode and transfer %d data to a off-chip master device.\n", TEST_COUNT);
printf("In the meanwhile the SPI controller will receive %d data from the off-chip master device.\n", TEST_COUNT);
printf("After the transfer is done, the %d received data will be printed out.\n", TEST_COUNT);
for(u32TxDataCount = 0; u32TxDataCount < TEST_COUNT; u32TxDataCount++)
{
/* Write the initial value to source buffer */
g_au32SourceData[u32TxDataCount] = 0x00AA0000 + u32TxDataCount;
/* Clear destination buffer */
g_au32DestinationData[u32TxDataCount] = 0;
}
u32TxDataCount = 0;
u32RxDataCount = 0;
printf("Press any key if the master device configuration is ready.\n");
getchar();
printf("\n");
/* Access TX and RX FIFO */
while(u32RxDataCount < TEST_COUNT)
{
/* Check TX FULL flag and TX data count */
if(((SPI0->STATUS & SPI_STATUS_TX_FULL_Msk) == 0) && (u32TxDataCount < TEST_COUNT))
SPI0->TX0 = g_au32SourceData[u32TxDataCount++]; /* Write to TX FIFO */
/* Check RX EMPTY flag */
if((SPI0->STATUS & SPI_STATUS_RX_EMPTY_Msk) == 0)
g_au32DestinationData[u32RxDataCount++] = SPI0->RX0; /* Read RX FIFO */
}
/* Print the received data */
printf("Received data:\n");
for(u32RxDataCount = 0; u32RxDataCount < TEST_COUNT; u32RxDataCount++)
{
printf("%d:\t0x%X\n", u32RxDataCount, g_au32DestinationData[u32RxDataCount]);
}
printf("The data transfer was done.\n");
printf("\n\nExit SPI driver sample code.\n");
/* Disable SPI0 peripheral clock */
CLK->APBCLK &= (~CLK_APBCLK_SPI0_EN_Msk);
while(1);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable external 12MHz XTAL */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
/* Select HXT as the clock source of HCLK */
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HXT;
/* Select HXT as the clock source of UART; select HCLK as the clock source of SPI0. */
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~(CLK_CLKSEL1_UART_S_Msk | CLK_CLKSEL1_SPI0_S_Msk))) | (CLK_CLKSEL1_UART_S_HXT | CLK_CLKSEL1_SPI0_S_HCLK);
/* Enable UART0 and SPI0 clock */
CLK->APBCLK = CLK_APBCLK_UART0_EN_Msk | CLK_APBCLK_SPI0_EN_Msk;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CyclesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Setup SPI0 multi-function pins */
SYS->P1_MFP = SYS_MFP_P14_SPISS0 | SYS_MFP_P15_MOSI_0 | SYS_MFP_P16_MISO_0 | SYS_MFP_P17_SPICLK0;
}
void UART0_Init(void)
{
/* Word length is 8 bits; 1 stop bit; no parity bit. */
UART0->LCR = UART_LCR_WLS_Msk;
/* Using mode 2 calculation: UART bit rate = UART peripheral clock rate / (BRD setting + 2) */
/* UART peripheral clock rate 12MHz; UART bit rate 115200 bps. */
/* 12000000 / 115200 bps ~= 104 */
/* 104 - 2 = 0x66. */
UART0->BAUD = UART_BAUD_DIV_X_EN_Msk | UART_BAUD_DIV_X_ONE_Msk | (0x66);
}
void SPI_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init SPI */
/*---------------------------------------------------------------------------------------------------------*/
/* Configure SPI0 as a slave, clock idle low, 32-bit transaction, drive output on falling clock edge and latch input on rising edge. */
SPI0->CNTRL = SPI_CNTRL_FIFO_Msk | SPI_CNTRL_SLAVE_Msk | SPI_CNTRL_TX_NEG_Msk;
/* Configure SPI0 as a low level active device. */
SPI0->SSR = SPI_SSR_SS_LTRIG_Msk;
/* Set IP clock divider. SPI peripheral clock rate = HCLK / 2 = 6MHz */
SPI0->DIVIDER = 0;
}
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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