本帖最后由 myic200610 于 2012-3-4 22:58 编辑
下面的一段话来自铁电存储器FM1808的英文手册（参见附图），请高手帮我翻译下。
非常感谢！
F-RAM memories do not need this system overhead. The memory will not block access at any VDD level. The user, however, should prevent the processor from accessing memory when VDD is out-of-tolerance. The common design practice of holding a processor in reset during powerdown may be sufficient. It is recommended that Chip Enable is pulled high and allowed to track VDD during powerup and powerdown cycles.It is the user’s responsibility to ensure that chip enable is high to prevent accesses below VDD min. (4.5V). Figure 3 shows a pullup resistor on /CE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition.The pullup resistor value should be chosen to ensure the /CE pin tracks VDD yet a high enough value that the current drawn when /CE is low is not an issue.
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