module ft60x_top(
input sys_clk_i,//50mINPUT
// system control
input Rstn_i,//fpga reset
output USBSS_EN,//power enable
output wire LED_o,
// FIFO interface
(*mark_debug = "true"*)(* KEEP = "TRUE" *)input CLK_i,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)inout [7:0] DATA_io7_0,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)inout [7:0] DATA_io15_8,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)inout [7:0] DATA_io23_16,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)inout [7:0] DATA_io31_24,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)inout [3:0] BE_io,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)input wire RXF_N_i, // ACK_N
(*mark_debug = "true"*)(* KEEP = "TRUE" *)input wire TXE_N_i,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output reg OE_N_o,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output reg WR_N_o, // REQ_N
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output SIWU_N_o,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output reg RD_N_o,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output WAKEUP_o,
(*mark_debug = "true"*)(* KEEP = "TRUE" *)output [1:0] GPIO_o
);
assign USBSS_EN = 1'b1;
assign WAKEUP_o = 1'b1;
assign GPIO_o = 2'b10;//00:245模式;11:4通道模式
assign SIWU_N_o = 1'b0;
//assign DATA_io7_0=8'hff;
//assign DATA_io23_16=8'hff;
//assign DATA_io31_24=8'hff;
//assign OE_N_o=0;//245模式下有用
//assign RD_N_o=0;//245模式下有用
wire rstn;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) wire [35:0] FIFO_Din;
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [35:0] FIFO_Dout;
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [7:0] data_out7_0;//总线往外输出的数据组，可以为指令或输出数据
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [7:0] data_out15_8;
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [7:0] data_out23_16;
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [7:0] data_out31_24;
(*mark_debug = "true"*)(* KEEP = "TRUE" *)wire [3:0] Be_out;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) reg [7:0] commond_out7_0;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) reg [7:0] commond_out15_8;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) reg [7:0] commond_out23_16;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) reg [7:0] commond_out31_24;
(*mark_debug = "true"*)(* KEEP = "TRUE" *) reg [3:0] commond_Be_out;
(*mark_debug = "true"*) (* KEEP = "TRUE" *) wire [3 :0] BE_RD;
(*mark_debug = "true"*) reg [ 3:0] BE_WR;
(*mark_debug = "true"*) wire FIFO_F,FIFO_V;
(*mark_debug = "true"*) reg [7:0] mode4ch_state;
(*mark_debug = "true"*) wire FIFO_WR;
(*mark_debug = "true"*) wire FIFO_RD;
assign FIFO_Din = ((!RXF_N_i)&&( mode4ch_state==8'd3)) ? {BE_io,DATA_io31_24,DATA_io23_16,DATA_io15_8,DATA_io7_0} : 36'd0;//read data dir
assign FIFO_WR =((!RXF_N_i)&&( mode4ch_state==8'd3)) ? 1'd1:1'd0;
assign FIFO_RD =((TXE_N_i)&&(!RXF_N_i)&&(mode4ch_state==8'd7)) ? 1'd1:1'd0;
assign DATA_io7_0 = ((TXE_N_i)&&(mode4ch_state==8'd3)) ? 8'bz: data_out7_0 ;
assign DATA_io15_8 = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? data_out15_8:8'bz ;
assign DATA_io23_16 = ((TXE_N_i)&&(mode4ch_state==8'd3)) ? 8'bz: data_out23_16 ;
assign DATA_io31_24 = ((TXE_N_i)&&(mode4ch_state==8'd3)) ? 8'bz: data_out31_24 ;
assign BE_io = ((TXE_N_i)&&(mode4ch_state==8'd3)) ? 4'bz : Be_out;// write data
//assign data_out = (!TXE_N_i) ? commond_out:FIFO_Dout;// write data dir
//assign data_out7_0 = (!RXF_N_i && ()mode4ch_state==8'd7) ? FIFO_Dout[7:0] :commond_out7_0;// write data dir
//assign data_out15_8 = (!RXF_N_i && mode4ch_state==8'd7) ? FIFO_Dout[15:8] :commond_out15_8;
//assign data_out23_16 = (!RXF_N_i && mode4ch_state==8'd7) ? FIFO_Dout[23:16]:commond_out23_16;
//assign data_out31_24 = (!RXF_N_i && mode4ch_state==8'd7) ? FIFO_Dout[31:24]:commond_out31_24;
//assign Be_out = (!RXF_N_i && mode4ch_state==8'd7) ? FIFO_Dout[35:32]:commond_Be_out;
assign data_out7_0 = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? FIFO_Dout[7:0] :commond_out7_0;// write data dir
assign data_out15_8 = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? FIFO_Dout[15:8] :commond_out15_8;
assign data_out23_16 = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? FIFO_Dout[23:16]:commond_out23_16;
assign data_out31_24 = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? FIFO_Dout[31:24]:commond_out31_24;
assign Be_out = ((TXE_N_i)&&(mode4ch_state==8'd7 || mode4ch_state==8'd6)) ? FIFO_Dout[35:32]:commond_Be_out;
//assign BE_RD = (mode4ch_state==2'd1) ? BE_io : 4'd0;
//assign FIFO_RD = (!WR_N_o)&&(!TXE_N_i);
reg RXF_N_i_r0;
always @(posedge CLK_i)begin
RXF_N_i_r0 <= RXF_N_i;
end
reg [7:0] data_ch;
reg [15:0] test_cnt;
always @(posedge CLK_i)begin
if(!rstn)begin
mode4ch_state <= 8'd1;
test_cnt<=8'd0;
data_ch<=8'd1;
commond_out7_0<=8'hff;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'hf;
WR_N_o <= 1'b1;
end
else begin
case(mode4ch_state)
1:begin
if(RXF_N_i && DATA_io15_8==8'hef)begin//通道1数据写入FPGA请求
WR_N_o <= 1'b0;
data_ch<=8'd1;
mode4ch_state<=8'd2;
commond_out7_0<=8'h01;//1通道
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'h0;
end
else if(RXF_N_i && DATA_io15_8==8'hdf)begin//通道2数据写入FPGA请求
WR_N_o <= 1'b0;
data_ch<=8'd2;
mode4ch_state<=8'd2;
commond_out7_0<=8'h02;//2通道
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'h0;
end
else if(RXF_N_i && DATA_io15_8==8'hfe)begin//通道1数据可以读出FPGA
WR_N_o <= 1'b0;
data_ch<=8'd1;
mode4ch_state<=8'd5;//跳转到状态机5执行数据读出
commond_out7_0<=8'h01;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'h1;
end
else if(RXF_N_i && DATA_io15_8==8'hfd)begin//通道2数据可以读出FPGA
WR_N_o <= 1'b0;
data_ch<=8'd2;
mode4ch_state<=8'd5;
commond_out7_0<=8'h02;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'h1;
end
else begin
WR_N_o <= 1'b1; //请求读取数据，
commond_out7_0<=8'hff;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'hf;
end
end
2:begin
if(TXE_N_i)begin
mode4ch_state<=8'd3;
end
end
3:begin
if(!RXF_N_i_r0 && RXF_N_i)begin
mode4ch_state<=8'd1;
end
end
4:begin//FPGA读数据状态，通过RXF_N确定数据段
// if(test_cnt==16'd700) begin//TXE_N_i抬高时数据已经全部的完成
if(RXF_N_i && DATA_io15_8==8'hfe)begin
WR_N_o <= 1'b0;
mode4ch_state<=8'd5;
commond_out7_0<=8'h01;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'h1;
end
else begin
WR_N_o <= 1'b1; //请求读取数据，
commond_out7_0<=8'hff;
commond_out23_16<=8'hff;
commond_out31_24<=8'hff;
commond_Be_out<=4'hf;
end
end
5:begin
// if(TXE_N_i)begin
mode4ch_state<=8'd6;
// end
end
6:begin
// if(!RXF_N_i_r0 && RXF_N_i)begin
mode4ch_state<=8'd7;
end
7:begin
if(!RXF_N_i_r0 && RXF_N_i)begin
mode4ch_state<=8'd1;
end
end
endcase
end
end
led_running led_running(
.clk(CLK_i),
.RSTn(rstn),
.led_out(LED_o)
);
// fifo master
wire [35:0] FIFO_Dout_ch1,FIFO_Dout_ch2;
assign FIFO_Dout= (data_ch==8'd1) ? FIFO_Dout_ch1:FIFO_Dout_ch2;
//assign FIFO_Dout= 36'hfffffffff;
wire [15:0] data_count_ch1,data_count_ch2;
fifo_generator_0 fifo_inst_ch1 (
.clk(CLK_i), // input wire clk
.srst(!rstn), // input wire srst
.din(FIFO_Din), // input wire [15 : 0] din
.wr_en(FIFO_WR && data_ch==8'd1), // input wire wr_en
.rd_en(FIFO_RD && data_ch==8'd1), // input wire rd_en
.dout(FIFO_Dout_ch1), // output wire [15 : 0] dout
.full(FIFO_F), // output wire full
// .empty(FIFO_E), // output wire empty
.valid(FIFO_V), // output wire valid
.data_count(data_count_ch1)
);
fifo_generator_0 fifo_inst_ch2 (
.clk(CLK_i), // input wire clk
.srst(!rstn), // input wire srst
.din(FIFO_Din), // input wire [15 : 0] din
.wr_en(FIFO_WR && data_ch==8'd2), // input wire wr_en
.rd_en(FIFO_RD && data_ch==8'd2), // input wire rd_en
.dout(FIFO_Dout_ch2), // output wire [15 : 0] dout
.full(), // output wire full
// .empty(FIFO_E), // output wire empty
.valid(), // output wire valid
.data_count(data_count_ch2)
);
ila_0 ila_0 (
.clk(CLK_i),
.probe0({RXF_N_i,TXE_N_i,WR_N_o,RD_N_o,mode4ch_state[2:0],FIFO_WR,test_cnt}),
//.probe1({DATA_io7_0,DATA_io15_8,DATA_io23_16,DATA_io31_24,BE_io}),
.probe1({FIFO_Din,FIFO_WR,FIFO_RD,FIFO_Dout_ch1}),
.probe2({data_count_ch1,data_count_ch2})
);
Delay_rst #(
.num(20'hffff0)
)
Delay_rst_inst
(
.clk_i(CLK_i),
.rstn_i(Rstn_i),
.rst_o(rstn)
);
//assign rstn=Rstn_i;
endmodule
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