本帖最后由 NICKY99 于 2012-3-15 09:34 编辑
各位好！
以下为SC16IS750程序，此程序要实现全双工UART，但以下程序只有发送正常，接收不正常，请各位指出问题所在，谢谢！
//**************************************************
// sc16is750
//**************************************************
void Init_750SPI(void)
{
DDRB|=(1<<CS_MOSI)|(1<<CS_SCK)|(1<<CS_CS);
SPCR|=(1<<SPE)|(1<<MSTR)|(1<<SPR1)|(1<<SPR0); //SPI模式0
SPSR = 0x00; //setup SPI
SET_BIT(PORTB,CS_DRDY);
SET_BIT(PORTB,CS_MISO);
}
/*******************************************/
void Wreg(unsigned char addr,unsigned char regdata) //写寄存器
{
CLR_BIT(PORTE,COM_CS);
SPDR = (addr<<3);
while(!(SPSR&(1<<SPIF)));
SPDR = regdata;
while(!(SPSR&(1<<SPIF)));
SET_BIT(PORTE,COM_CS);
}
/*******************************************/
unsigned char Rreg(unsigned char addr) //读寄存器
{
CLR_BIT(PORTE,COM_CS);
SPDR = (0x80|(addr<<3));
while(!(SPSR&(1<<SPIF)));
SPDR = 0x00;//启动SPI
while(!(SPSR&(1<<SPIF)));
SET_BIT(PORTE,COM_CS);
return SPDR;
}
unsigned char ReadData(void)
{
CLR_BIT(PORTE,COM_CS);
SPDR =(0x80|( (RHR<<3));
while(!(SPSR&(1<<SPIF)));
SPDR = 0x00;//启动SPI
while(!(SPSR&(1<<SPIF)));
SET_BIT(PORTE,COM_CS);
return SPDR;
}
/*********************************************/
void Spi_Send(unsigned char addr,unsigned char senddata)
{
CLR_BIT(PORTE,COM_CS);
SPDR = (addr<<3);
while(!(SPSR&(1<<SPIF)));
SPDR = senddata;
while(!(SPSR&(1<<SPIF)));
SET_BIT(PORTE,COM_CS);
}
void Spi_sendstring(unsigned char *sdata,unsigned int amount)
{
CLR_BIT(PORTE,COM_CS);
SPDR = (THR<<3); // 传送命令到SPI寄存器
while(amount)
{
while(!(SPSR&(1<<SPIF)));
SPDR = *sdata; sdata++;
amount--;
}
while(!(SPSR&(1<<SPIF)));
SET_BIT(PORTE,COM_CS);
}
/*******************************************/
void Init_750(void)
{
CLR_BIT(PORTC,COM_RST);
_delay_ms(20);
SET_BIT(PORTC,COM_RST);
_delay_ms(10);
Wreg(IOIntEna,0x00); //使能IO中断
_delay_ms(10);
Wreg (LCR, 0x80);// 0x80 to program baud rate
_delay_ms(10);
Wreg (DLL, 0x06);// 0x30=19.2K, 0x08 =115.2K with X1=14.7456 MHz 0x60=1200 with x1=1.8432MHz
_delay_ms(10);
Wreg (DLH, 0x00);// divisor = 0x0008 for 115200 bps
_delay_ms(10);
//Wreg (LCR, 0xBF);// access EFR register
//Wreg (EFR, 0X10);// enable enhanced registers
Wreg (LCR, 0x03);// 8 data bit, 1 stop bit, no parity
_delay_ms(10);
Wreg (FCR, 0x06);// reset TXFIFO, reset RXFIFO, non FIFO mode
_delay_ms(10);
Wreg (FCR, 0xb7);// enable FIFO mode
_delay_ms(10);
Wreg (IER, 0x05);//
} |
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