void TmrFeqSet(TMR_Type *TIMx,uint32_t Ferq ,FunctionalState NewState)
{
TMR_TimerBaseInitType TMR_TMReBaseStructure;
uint32_t uiTIMxCLK;
uint16_t usPeriod;
uint16_t usPrescaler;
//ÔÝÍ£¶¨Ê±Æ÷
TMR_Cmd(TIMx, DISABLE);
/* APB ¶¨Ê±Æ÷ */
uiTIMxCLK = SystemCoreClock;
//
if (Ferq < 100)
{
usPrescaler = 10000 - 1; /* ·ÖƵ±È = 1000 */
usPeriod = (uiTIMxCLK / 10000) / Ferq - 1; /* ×Ô¶¯ÖØ×°µÄÖµ */
}
else if (Ferq < 5000)
{
usPrescaler = 100 - 1; /* ·ÖƵ±È = 100 */
usPeriod = (uiTIMxCLK / 100) / Ferq - 1; /* ×Ô¶¯ÖØ×°µÄÖµ */
}
else /* ´óÓÚ5KµÄƵÂÊ£¬ÎÞÐè·ÖƵ */
{
usPrescaler = 0; /* ·ÖƵ±È = 1 */
usPeriod = uiTIMxCLK / Ferq - 1; /* ×Ô¶¯ÖØ×°µÄÖµ */
}
//
TMR_TimeBaseStructInit(&TMR_TMReBaseStructure);
TMR_SetCounter(TIMx, 0);
//
TMR_TMReBaseStructure.TMR_Period = usPeriod;
TMR_TMReBaseStructure.TMR_DIV = usPrescaler;
TMR_TMReBaseStructure.TMR_ClockDivision = 0;
TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up | (1<<2);
//
TMR_TimeBaseInit(TIMx, &TMR_TMReBaseStructure);
//
TMR_ARPreloadConfig(TIMx,ENABLE);
/* Prescaler configuration */
TMR_DIVConfig(TIMx, usPrescaler, TMR_DIVReloadMode_Immediate);
/* TMR IT enable */
TMR_INTConfig(TIMx, TMR_INT_Overflow, NewState);
//
TMR_ClearITPendingBit(TIMx, TMR_INT_Overflow);
/* TMR2 enable counter */
TMR_Cmd(TIMx, NewState);
}
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