`timescale 1ns/1ps
module otsu_yuzhi(
input wire clk,
input wire rst,
input wire[7:0] data_in,
//input wire de,
output reg[7:0] threshold,
output wire[7:0] data_out,
input hd_hs,
input hd_vs,
input hd_de,
output reg yuzhi_hs,
output reg yuzhi_vs,
output reg yuzhi_de
);
parameter data_cnt_max = 24'd786432;
parameter time_max = 28'd201326592;
reg[7:0] T;
reg[23:0] data_cnt;
reg[27:0] data0;
reg[27:0] data1;
reg[27:0] data_01;
reg[23:0] data0_cnt;
reg[23:0] data1_cnt;
reg[23:0] w0;
reg[23:0] w1;
reg[27:0] u0;
reg[27:0] u1;
reg[27:0] u;
wire[27:0] g;
reg[27:0] g2;
reg[27:0] max;
reg[27:0] time_cnt;
//数据计数
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
data_cnt<=24'd0;
else if(data_cnt == data_cnt_max-1)
data_cnt<=24'd0;
else
data_cnt<=data_cnt + 24'd1;
end
//总时间计数
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
time_cnt<=28'd0;
else if(time_cnt == time_max-1)
time_cnt<=28'd0;
else
time_cnt<=time_cnt + 28'd1;
end
//阈值计数
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
T <=8'd0;
else if(data_cnt <= data_cnt_max - 1)
T <=T + 8'd1;
else
T <= T;
end
//1/0数据总和
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
data1 <=28'd0;
else if(data_in>=T)
data1 <= data1 + data_in;
else
data1 <= data1;
end
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
data0 <=28'd0;
else if(data_in<T)
data0 <= data0 + data_in;
else
data0 <= data0;
end
//0/1计数
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
data1_cnt <=24'd0;
else if(data_in>=T)
data1_cnt <= data1_cnt + 24'd1;
else
data1_cnt <= data1_cnt;
end
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
data0_cnt <=24'd0;
else if(data_in<T)
data0_cnt <= data0_cnt + 24'd1;
else
data0_cnt <= data0_cnt;
end
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
begin
data_01 <= 28'd0;
u0 <= 28'd0;
u1 <= 28'd0;
w0 <= 28'd0;
w1 <= 28'd0;
u <= 28'd0;
end
else if(data_cnt == data_cnt_max -1)
begin
data_01 <= data0 + data1;
u0 <= data0/data_01;
u1 <= data1/data_01;
w0 <= data0_cnt/data_cnt_max;
w1 <= data1_cnt/data_cnt_max;
u <= data_01/data_cnt_max - 1;
end
// else
//begin
// data_01 <= 28'd0;
// u0 <= 28'd0;
// u1 <= 28'd0;
// w0 <= 28'd0;
// w1 <= 28'd0;
// u <= 28'd0;
//end
end
assign g =w0*(u0-u)^2 + w1*(u1-u)^2;
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
g2 <=28'd0;
else if (g > g2)
g2 <= g;
else
g2 <= g2;
end
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
max <=28'd0;
else if (time_cnt == time_max)
max <= g2;
else
max <= max;
end
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
threshold <=28'd0;
else if (g2 == max)
threshold <= T;
else
threshold <= threshold;
end
assign data_out = (data_in > threshold) ? 8'h00 : 8'hff;
reg i_h_sync_delay_1;
reg i_v_sync_delay_1;
reg i_data_en_delay_1;
reg i_h_sync_delay_2;
reg i_v_sync_delay_2;
reg i_data_en_delay_2;
reg i_h_sync_delay_3;
reg i_v_sync_delay_3;
reg i_data_en_delay_3;
always@(posedge clk or posedge rst)
begin
if(rst == 1'b1)
begin
i_h_sync_delay_1 <= 1'b0;
i_v_sync_delay_1 <= 1'b0;
i_data_en_delay_1 <= 1'b0;
i_h_sync_delay_2 <= 1'b0;
i_v_sync_delay_2 <= 1'b0;
i_data_en_delay_2 <= 1'b0;
i_h_sync_delay_3 <= 1'b0;
i_v_sync_delay_3 <= 1'b0;
i_data_en_delay_3 <= 1'b0;
yuzhi_hs <= 1'b0;
yuzhi_vs <= 1'b0;
yuzhi_de <= 1'b0;
end
else
begin
i_h_sync_delay_1 <= hd_hs;
i_v_sync_delay_1 <= hd_vs;
i_data_en_delay_1 <= hd_de;
i_h_sync_delay_2 <= i_h_sync_delay_1;
i_v_sync_delay_2 <= i_v_sync_delay_1;
i_data_en_delay_2 <= i_data_en_delay_1;
i_h_sync_delay_3 <= i_h_sync_delay_2;
i_v_sync_delay_3 <= i_v_sync_delay_2;
i_data_en_delay_3 <= i_data_en_delay_2;
yuzhi_hs <= i_h_sync_delay_3;
yuzhi_vs <= i_v_sync_delay_3;
yuzhi_de <= i_data_en_delay_3;
end
end
endmodule
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