#define SPC3_1_RST_H() my_set_port_pin(2, 30, 1) //p2.30
#define SPC3_1_RST_L() my_set_port_pin(2, 30, 0)
#define SPC3_2_RST_H() my_set_port_pin(2, 12, 1) //p2.12
#define SPC3_2_RST_L() my_set_port_pin(2, 12, 0)
#define SPC3_1_RAM_BASE_ADDR 0x81000000 //spc3_1 ram start address
#define SPC3_2_RAM_BASE_ADDR 0x80000000 //spc3_2 ram start address
#define EMCStaticCFG0 0x80
#define EMCStaticWaitWen0 0
#define EMCStaticWaitWr0 8
#define EMCStaticWaitOen0 0
#define EMCStaticWaitRd0 8
#define EMCStaticWaitTurn0 0x0F
#define EMCStaticExtendWait 4
void Init_SPC3_1(void)
{
//reset the spc3
SPC3_1_RST_L();
cyg_thread_delay(10);
SPC3_1_RST_H();
hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_EMC, 1);
HAL_WRITE_UINT32(LPC24_EMCControl, 0x01); //enable EMC
//HAL_WRITE_UINT32(LPC24_EMCStaticExtendWait, EMCStaticExtendWait);
HAL_WRITE_UINT32(LPC24_EMCStaticCFG1, EMCStaticCFG0);
HAL_WRITE_UINT32(LPC24_EMCStaticWaitWen1, EMCStaticWaitWen0);
HAL_WRITE_UINT32(LPC24_EMCStaticWaitOen1, EMCStaticWaitOen0);
HAL_WRITE_UINT32(LPC24_EMCStaticWaitRd1, EMCStaticWaitRd0);
HAL_WRITE_UINT32(LPC24_EMCStaticWaitWr1, EMCStaticWaitWr0);
HAL_WRITE_UINT32(LPC24_EMCStaticWaitTurn1, EMCStaticWaitTurn0);
}
void test1(void)
{
INT32U i;
INT8U val;
for(i=0; i <10; i++)
{
HAL_WRITE_UINT8(SPC3_1_RAM_BASE_ADDR+40+i, 0xaa);//min 125nS between read/write cycle
}
for(i=0; i <10; i++)
{
HAL_READ_UINT8(SPC3_1_RAM_BASE_ADDR+40+i, val);
hld_reg[200+i] = (INT16U)val;
}
} |