HC32F460 RTC掉电重启

只看该作者 · 2022-6-23 14:38

问题1. RTC掉电重启之后M4_RTC->CR1_f.START判断为需要复位。
问题2. PowerDown1和2模式下，掉电第二次，再也无法唤醒，必须彻底断电才能重新来。而PowerDown3和4模式无此问题。

只看该作者 · 2022-6-23 14:53

void Power_Callback(void)
{
if(PORT_GetBit(POWER_PORT, POWER_PIN) == Reset)
{
BSP_LED_On(LED_RED);
printf("Enter Power down!\r\n");
SDIOC_DeInit(M4_SDIOC1); //SDIO
DMA_DeInit(M4_DMA1, DmaCh0); //SDIO
DMA_DeInit(ULOG_DMA_UNIT, ULOG_DMA_CH); //ULOG
hd_usb_dev_deinit(&usb_dev);

/* Wait for RTC to work properly before switching to low power */
if (RTC_LowPowerSwitch() != Ok)
{
      DDL_Printf("switch to low power failed!\r\n");
}

BSP_LED_Off(LED_RED);
BSP_LED_Off(LED_BLUE);

PWC_EnterPowerDownMd();
}
EXINT_Irq**Clr(POWER_EXTI_CH);
}

void Power_Init(void)
{
stc_pwc_pwr_mode_cfg_t  stcPwcPwrMdCfg;
stc_exint_config_t stcExtiConfig;
stc_irq_regi_conf_t stcIrqRegiConf;
stc_port_init_t stcPortInit;

/* configuration structure initialization */
MEM_ZERO_STRUCT(stcPwcPwrMdCfg);
MEM_ZERO_STRUCT(stcExtiConfig);
MEM_ZERO_STRUCT(stcIrqRegiConf);
MEM_ZERO_STRUCT(stcPortInit);

PORT_SetFunc(POWER_PORT, POWER_PIN, Func_Gpio, Disable);

/* Config power down mode. */
stcPwcPwrMdCfg.enPwrDownMd = PowerDownMd2;
stcPwcPwrMdCfg.enRLdo = Disable;
stcPwcPwrMdCfg.enIoRetain = IoPwrDownRetain;
stcPwcPwrMdCfg.enRetSram = Disable;
stcPwcPwrMdCfg.enPwrDWkupTm = Vcap0047;
PWC_PowerModeCfg(&stcPwcPwrMdCfg);

PWC_Xtal32CsCmd(Enable);

/* wake_up 1_2 event */
PWC_PdWakeupEvtEdgeCfg(PWC_PDWKUP_EDGE_WKP0, EdgeRising);
PWC_PdWakeup0Cmd(PWC_PDWKEN0_WKUP03,Enable);
PWC_ClearWakeup0Flag(PWC_PTWK0_WKUPFLAG);

/**************************************************************************/
/* External Int Ch.03 for power                                        */
/**************************************************************************/
stcExtiConfig.enExitCh = POWER_EXTI_CH;

/* Filter setting */
stcExtiConfig.enFilterEn = Disable;
stcExtiConfig.enFltClk = Pclk3Div8;
/* falling edge for keyscan function */
stcExtiConfig.enExtiLvl = ExIntLowLevel;
EXINT_Init(&stcExtiConfig);

/* Set PB3 as External Int Ch.03 input */
stcPortInit.enExInt = Enable;
stcPortInit.enPullUp = Disable;
PORT_Init(POWER_PORT, POWER_PIN, &stcPortInit);

/* Select External Int Ch.03 */
stcIrqRegiConf.enIntSrc = POWER_INT_PORT;

/* Register External Int to Vect.No.007 */
stcIrqRegiConf.enIRQn = Int007_IRQn;

/* Callback function */
stcIrqRegiConf.pfnCallback = &Power_Callback;

/* Registration IRQ */
enIrqRegistration(&stcIrqRegiConf);

/* Clear pending */
NVIC_ClearPendingIRQ(stcIrqRegiConf.enIRQn);

/* Set priority */
NVIC_SetPriority(stcIrqRegiConf.enIRQn, DDL_IRQ_PRIORITY_00);

/* Enable NVIC */
NVIC_EnableIRQ(stcIrqRegiConf.enIRQn);
}

void Rtc_Config(void)
{
stc_rtc_init_t       stcRtcInit;
stc_irq_regi_conf_t    stcIrqRegiConf;

MEM_ZERO_STRUCT(stcRtcInit);
MEM_ZERO_STRUCT(stcIrqRegiConf);

/* Configure interrupt of rtc period */
stcIrqRegiConf.enIntSrc = INT_RTC_PRD;
stcIrqRegiConf.enIRQn = Int006_IRQn;
stcIrqRegiConf.pfnCallback = &RtcPeriod_IrqCallback;
enIrqRegistration(&stcIrqRegiConf);
NVIC_ClearPendingIRQ(stcIrqRegiConf.enIRQn);
NVIC_SetPriority(stcIrqRegiConf.enIRQn, DDL_IRQ_PRIORITY_DEFAULT);
NVIC_EnableIRQ(stcIrqRegiConf.enIRQn);

/* Rtc stopped */
if (0u == M4_RTC->CR1_f.START)
{
DDL_Printf("RTC Deinit!\r\n");
/* Reset rtc counter */
if (RTC_DeInit() == ErrorTimeout)
{
DDL_Printf("reset rtc failed!\r\n");
}
else
{
/* Configuration rtc structure */
stcRtcInit.enClkSource = RtcClkXtal32;
stcRtcInit.enPeriodInt = RtcPeriodIntOneSec;
stcRtcInit.enTimeFormat = RtcTimeFormat24Hour;
stcRtcInit.enCompenWay = RtcOutputCompenDistributed;
stcRtcInit.enCompenEn = Disable;
stcRtcInit.u16CompenVal = 0u;
RTC_Init(&stcRtcInit);

/* Enable period interrupt */
RTC_IrqCmd(RtcIrqPeriod, Enable);
/* Startup rtc count */
RTC_Cmd(Enable);
}
}
}

void BSP_CLK_Init(void)
{

stc_clk_sysclk_cfg_t stcSysClkCfg;
stc_clk_xtal_cfg_t    stcXtalCfg;
stc_clk_xtal32_cfg_t stcXtal32Cfg;
stc_clk_mpll_cfg_t    stcMpllCfg;
stc_sram_config_t    stcSramConfig;

MEM_ZERO_STRUCT(stcSysClkCfg);
MEM_ZERO_STRUCT(stcXtalCfg);
MEM_ZERO_STRUCT(stcXtal32Cfg);
MEM_ZERO_STRUCT(stcMpllCfg);
MEM_ZERO_STRUCT(stcSramConfig);

/* Set bus clk div. */
stcSysClkCfg.enHclkDiv  = ClkSysclkDiv1;
stcSysClkCfg.enExclkDiv = ClkSysclkDiv2;
stcSysClkCfg.enPclk0Div = ClkSysclkDiv1;
stcSysClkCfg.enPclk1Div = ClkSysclkDiv2;
stcSysClkCfg.enPclk2Div = ClkSysclkDiv4;
stcSysClkCfg.enPclk3Div = ClkSysclkDiv4;
stcSysClkCfg.enPclk4Div = ClkSysclkDiv2;
CLK_SysClkConfig(&stcSysClkCfg);

/* Config Xtal and Enable Xtal */
stcXtalCfg.enMode = ClkXtalModeOsc;
stcXtalCfg.enDrv = ClkXtalLowDrv;
stcXtalCfg.enFastStartup = Enable;
CLK_XtalConfig(&stcXtalCfg);
CLK_XtalCmd(Enable);

/* Config Xtal32 and Enable Xtal32 */
CLK_Xtal32Cmd(Disable);
Ddl_Delay1ms(100u);
stcXtal32Cfg.enDrv = ClkXtal32HighDrv;
stcXtal32Cfg.enFilterMode = ClkXtal32FilterModeFull;
CLK_Xtal32Config(&stcXtal32Cfg);
CLK_Xtal32Cmd(Enable);

/* sram init include read/write wait cycle setting */
stcSramConfig.u8SramIdx = Sram12Idx | Sram3Idx | SramHsIdx | SramRetIdx;
stcSramConfig.enSramRC = SramCycle2;
stcSramConfig.enSramWC = SramCycle2;
SRAM_Init(&stcSramConfig);

/* flash read wait cycle setting */
EFM_Unlock();
EFM_SetLatency(EFM_LATENCY_5);
EFM_Lock();

/* MPLL config (XTAL / pllmDiv * plln / PllpDiv = 200M). */
stcMpllCfg.pllmDiv = 1ul;
stcMpllCfg.plln = 50ul;
stcMpllCfg.PllpDiv = 2ul;
stcMpllCfg.PllqDiv = 2ul;
stcMpllCfg.PllrDiv = 2ul;
CLK_SetPllSource(ClkPllSrcXTAL);
CLK_MpllConfig(&stcMpllCfg);

/* Enable MPLL. */
CLK_MpllCmd(Enable);
/* Wait MPLL ready. */
while(Set != CLK_GetFlagStatus(ClkFlagMPLLRdy))
{
;
}
/* Switch driver ability */
PWC_HS2HP();
/* Switch system clock source to MPLL. */
CLK_SetSysClkSource(CLKSysSrcMPLL);
}