////////////////////////////////////////
/*
fsmc 总线去读取 data_read高位时无法读取出来，一直是0。
这个总线读取是正确的，低16位正确的，高16位读不出来。
就是 12'd151:和12'd154 读回来的是0值，不知道是和原因
*/
module code_top(
clk_100,
rst_n,
csn,
rden,
wren,
CODE_A,
CODE_B,
CODE_Z,
address,
data_in,
data_out
);
assign wr = !(csn | wren);
assign rd = !(csn & rden);
input clk_100,rst_n,rden,wren;
input [3:0] CODE_A,CODE_B,CODE_Z;
input [11:0] address;
input [15:0] data_in;
output [15:0] data_out;
input csn;
wire [33:0] code_data[3:0];
wire [15:0] z_counter[3:0];
reg [33:0] data_read[3:0];
reg [15:0] z_read[3:0];
////////////////
encode code_x(
.clk_100M(clk_100),
.rst_n(rst_n),
.A_in(CODE_A[0]),
.B_in(CODE_B[0]),
.Z_in(CODE_Z[0]),
.code_data(code_data[0]),
.z_counter(z_counter[0])
);
////////////
reg [15:0]DB_OUT;
reg [15:0]data_read_h;
always @(rd or !rst_n)
begin
if(!rst_n)
begin
DB_OUT<=16'hzzzz;
data_read_h<= 16'h0;
end
else
begin
case (address)
12'd150:
begin
DB_OUT <= data_read[0][17:2];
data_read_h<= data_read[0][33:18];
end
12'd151:
begin
DB_OUT <=data_read_h; //x 16'd111;//
end
12'd152:DB_OUT <= z_read[0];
12'd153:
begin
DB_OUT <= data_read[1][17:2];
data_read_h<= data_read[1][33:18];
end
12'd154:
begin
DB_OUT <=data_read_h; //y code_data[1][33:18];//
end
12'd155:DB_OUT <=z_read[1];
12'd156:
begin
DB_OUT <= data_read[2][17:2];
data_read_h<= data_read[2][33:18];
end
default :
begin
DB_OUT <= 16'hzzzz;
code_data_h <= 16'h0000;
end
endcase
end
end
assign data_out = rd ? DB_OUT : 16'hzzzz;
always@(posedge clk_100 or negedge rst_n)
begin
if(!rst_n)
begin
data_read[0] <= 33'd0;
data_read[1] <= 33'd0;
data_read[2] <= 33'd0;
data_read[3] <= 33'd0;
z_read[0] <= 16'd0;
z_read[1] <= 16'd0;
z_read[2] <=16'd0;
z_read[3] <= 16'd0;
// code_data_h <= 16'h1;
end
else
begin
data_read[0] <= code_data[0];
data_read[1] <= code_data[1];
data_read[2] <= code_data[2];
data_read[3] <= code_data[3];
z_read[0] <= z_counter[0];
z_read[1] <= z_counter[1];
z_read[2] <= z_counter[2];
z_read[3] <= z_counter[3];
end
end
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