module comcase (
input wire a, b, c, d,
output reg e
);
always @(a or b or c or d)
case ({a, b})
2'b11: e = d;
2'b10: e = ~c;
2'b01: e = 1'b0;
2'b00: e = 1'b1;
endcase
endmodule
module compif (
input wire a, b, c, d,
output reg e
);
always @(a or b or c or d)
if (a & b)
e = d;
else if (a & ~b)
e = ~c;
else if (~a & b)
e = 1'b0;
else if (~a & ~b)
e = 1'b1;
endmodule
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