|
Root cause：W25Q256 status register 2 CMP bit set to 1 The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with TB, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by TB, BP3, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. The default setting is CMP=0. Solved by: clear the CMP bit, the flash turn to writable.
| 
楼主
标题置顶
标题高亮
