#include "six_step.h"
vu32 step = 1;
void six_step_init(void)
{
timer_oc_parameter_struct timer_ocintpara;
timer_parameter_struct timer_initpara;
timer_break_parameter_struct timer_breakpara;
rcu_periph_clock_enable(RCU_GPIOE);
rcu_periph_clock_enable(RCU_TIMER0);
rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_8);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_8);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_8);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_9);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_9);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_9);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_10);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_10);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_10);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_11);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_11);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_11);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_12);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_12);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_12);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_13);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_13);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_13);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_14);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_14);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_14);
gpio_mode_set(GPIOE,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_15);
gpio_output_options_set(GPIOE,GPIO_OTYPE_PP,GPIO_OSPEED_MAX,GPIO_PIN_15);
gpio_af_set(GPIOE,GPIO_AF_1,GPIO_PIN_15);
timer_initpara.alignedmode=TIMER_COUNTER_EDGE;
timer_initpara.clockdivision=TIMER_CKDIV_DIV1;
timer_initpara.counterdirection=TIMER_COUNTER_UP;
timer_initpara.period=599;
timer_initpara.prescaler=199;
timer_initpara.repetitioncounter=0;
timer_init(TIMER0,&timer_initpara);
timer_ocintpara.ocidlestate=TIMER_OC_IDLE_STATE_HIGH;
timer_ocintpara.ocnidlestate=TIMER_OCN_IDLE_STATE_HIGH;
timer_ocintpara.ocpolarity=TIMER_OC_POLARITY_HIGH;
timer_ocintpara.ocnpolarity=TIMER_OCN_POLARITY_HIGH;
timer_ocintpara.outputstate=TIMER_CCX_ENABLE;
timer_ocintpara.outputnstate=TIMER_CCXN_ENABLE;
timer_channel_output_config(TIMER0,TIMER_CH_0,&timer_ocintpara);
timer_channel_output_config(TIMER0,TIMER_CH_1,&timer_ocintpara);
timer_channel_output_config(TIMER0,TIMER_CH_2,&timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_0,299);
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_TIMING);
timer_channel_output_shadow_config(TIMER0,TIMER_CH_0,TIMER_OC_SHADOW_ENABLE);
timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_1,299);
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_TIMING);
timer_channel_output_shadow_config(TIMER0,TIMER_CH_1,TIMER_OC_SHADOW_ENABLE);
timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_2,299);
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_TIMING);
timer_channel_output_shadow_config(TIMER0,TIMER_CH_2,TIMER_OC_SHADOW_ENABLE);
timer_breakpara.runoffstate= TIMER_ROS_STATE_ENABLE;
timer_breakpara.ideloffstate= TIMER_IOS_STATE_ENABLE ;
timer_breakpara.deadtime= 164;
timer_breakpara.breakpolarity= TIMER_BREAK_POLARITY_LOW;
timer_breakpara.outputautostate= TIMER_OUTAUTO_ENABLE;
timer_breakpara.protectmode= TIMER_CCHP_PROT_OFF;
timer_breakpara.breakstate= TIMER_BREAK_ENABLE;
timer_break_config(TIMER0,&timer_breakpara);
timer_primary_output_config(TIMER0,ENABLE);
timer_interrupt_enable(TIMER0,TIMER_INT_CMT);
timer_interrupt_disable(TIMER0,TIMER_INT_BRK);
nvic_irq_enable(TIMER0_TRG_CMT_TIMER10_IRQn,1,1);
timer_enable(TIMER0);
}
void TIMER0_TRG_CMT_TIMER10_IRQHandler(void)
{
/* clear TIMER interrupt flag */
timer_interrupt_flag_clear(TIMER0,TIMER_INT_CMT);
switch(step){
/* next step: step 2 configuration .A-C` breakover---------------------------- */
case 1:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
step++;
break;
/* next step: step 3 configuration .B-C` breakover---------------------------- */
case 2:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_ENABLE);
step++;
break;
/* next step: step 4 configuration .B-A` breakover---------------------------- */
case 3:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 5 configuration .C-A` breakover---------------------------- */
case 4:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_ENABLE);
/* channel1 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_DISABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 6 configuration .C-B` breakover---------------------------- */
case 5:
/* channel0 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_2,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step++;
break;
/* next step: step 1 configuration .A-B` breakover---------------------------- */
case 6:
/* channel0 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCX_ENABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_0,TIMER_CCXN_DISABLE);
/* channel1 configuration */
timer_channel_output_mode_config(TIMER0,TIMER_CH_1,TIMER_OC_MODE_PWM0);
timer_channel_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_1,TIMER_CCXN_ENABLE);
/* channel2 configuration */
timer_channel_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCX_DISABLE);
timer_channel_complementary_output_state_config(TIMER0,TIMER_CH_2,TIMER_CCXN_DISABLE);
step = 1;
break;
}
}
static u32 delay;
void systick_config(void)
{
/* setup systick timer for 1000Hz interrupts */
if (SysTick_Config(SystemCoreClock / 100U)){
/* capture error */
while (1){
}
}
/* configure the systick handler priority */
NVIC_SetPriority(SysTick_IRQn, 0x00U);
}
/*!
\brief delay a time in milliseconds
\param[in] count: count in milliseconds
\param[out] none
\retval none
*/
void delay_1ms(uint32_t count)
{
delay = count;
while(0U != delay){
}
}
/*!
\brief delay decrement
\param[in] none
\param[out] none
\retval none
*/
void delay_decrement(void)
{
if (0U != delay){
delay--;
}
}
void SysTick_Handler(void)
{
timer_event_software_generate(TIMER0,TIMER_EVENT_SRC_CMTG);
}
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