HK32F030C8T6把OSC_IN和OSC_OUT作为普通的IO口使用

void SystemInit (void)

{    

  /* Set HSION bit */

  RCC->CR |= (uint32_t)0x00000001;

 

  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */

  RCC->CFGR &= (uint32_t)0xF8FFB80C;

  

  /* Reset HSEON, CSSON and PLLON bits */

  RCC->CR &= (uint32_t)0xFEF6FFFF;

 

  /* Reset HSEBYP bit */

  RCC->CR &= (uint32_t)0xFFFBFFFF;

 

  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */

  RCC->CFGR &= (uint32_t)0xFFC0FFFF;

 

  /* Reset PREDIV1[3:0] bits */

  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;

 

  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */

  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;

 

  /* Reset HSI14 bit */

  RCC->CR2 &= (uint32_t)0xFFFFFFFE;

 

  /* Disable all interrupts */

  RCC->CIR = 0x00000000;

 

  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */

  SetSysClock();

}

static void SetSysClock(void)

{

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

 

/******************************************************************************/

/*            PLL (clocked by HSE) used as System clock source                */

/******************************************************************************/

  

  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/

  /* Enable HSE */    

  //RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  RCC->CR &= ~((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;  

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

 

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }  

 

  if (HSEStatus == (uint32_t)0x01)

  {

    /* Enable Prefetch Buffer and set Flash Latency */

    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

 

    /* HCLK = SYSCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

      

    /* PCLK = HCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

 

    /* PLL configuration */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);

            

    /* Enable PLL */

    RCC->CR |= RCC_CR_PLLON;

 

    /* Wait till PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

 

    /* Select PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

 

    /* Wait till PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

    {

    }

  }

  else

  { /* If HSE fails to start-up, the application will have wrong clock 

         configuration. User can add here some code to deal with this error */

  }  

}