呼吸灯源代码

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zhaoqiansh| 初级技术员

楼主 | 2023-3-13 13:13 | 只看该作者回帖奖励

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代码, 呼吸灯, 源代码

module breath_led #(parameter LED_NUM = 4)(
input clk,
input rst_n,

output reg [LED_NUM-1:0] led
);

parameter time_us = 6'd50;
parameter time_ms = 10'd1000;
parameter time_s  = 10'd1000;

reg flag;
reg [3:0] led_r;

reg [5:0] cnt_us;
wire add_cnt_us;
wire end_cnt_us;

reg [9:0] cnt_ms;
wire add_cnt_ms;
wire end_cnt_ms;

reg [9:0] cnt_s;
wire add_cnt_s;
wire end_cnt_s;

always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
      cnt_us <= 0;
end
else if(add_cnt_us)begin
      if(end_cnt_us)begin
         cnt_us <= 6'd0;
      end
      else begin
         cnt_us <= cnt_us + 1'd1;
      end
end
else begin
      cnt_us <= cnt_us;
end
end

assign add_cnt_us = 1'b1;
assign end_cnt_us = add_cnt_us && cnt_us == time_us - 1'd1;

always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
      cnt_ms <= 0;
end
else if(add_cnt_ms)begin
      if(end_cnt_ms)begin
         cnt_ms <= 10'd0;
      end
      else begin
         cnt_ms <= cnt_ms + 1'd1;
      end
end
else begin
      cnt_ms <= cnt_ms;
end
end

assign add_cnt_ms = end_cnt_us;
assign end_cnt_ms = add_cnt_ms && cnt_ms == time_ms - 1'd1;

always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
      cnt_s <= 0;
end
else if(add_cnt_s)begin
      if(end_cnt_s)begin
         cnt_s <= 10'd0;
      end
      else begin
         cnt_s <= cnt_s + 1'd1;
      end
end
else begin
      cnt_s <= cnt_s;
end
end

assign add_cnt_s = end_cnt_ms;
assign end_cnt_s = add_cnt_s && cnt_s == time_s - 1'd1;

always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
      flag <= 1'b0;
end
else if(end_cnt_s)begin
      flag <= ~flag;
end
else begin
      flag <= flag;
end
end

always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
      led <= 4'b0;
      led_r <= 4'b1111;
end
else if(!flag)begin
      // led <= (cnt_s>cnt_ms)?1'b1:1'b0;
      if(cnt_s>cnt_ms)begin
         led <= led_r[LED_NUM - 1:0];
      end
      else
         led <= 4'b0;
end
else if(flag)begin
      // led <= (cnt_s>cnt_ms)?1'b0:1'b1;
      if(cnt_s<cnt_ms)begin
         led <= led_r[LED_NUM - 1:0];
      end
      else
         led <= 4'b0;
end
else
      led <= led;
end
endmodule

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