1、先贴CPLD的VHDL编程:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity stm32_cpld is
port(
cpld_cs:in std_logic;--cpld片选信号,硬件连接:通过SN74LVC4245与STM32的FSMC总线的 --FSMC_NE1(PD7)连接
rd:in std_logic; --读控制信号
wr:in std_logic;--写控制信号
cpld_rest:in std_logic;--复位信号
m_dir1:out std_logic;--控制U6(SN74LVC4245芯片)
m_dir2:out std_logic;--控制U7(SN74LVC4245芯片)
data_out:out std_logic_vector(7 downto 0) --8位数据输出
);
end stm32_cpld;
architecture behav of stm32_cpld is
signal data_buf:std_logic_vector(7 downto 0);
signal data_outctl:std_logic;
begin
m_dir1 <= '0';--控制SN74LVC4245,DIR=0,信号流向:B->A
m_dir2 <= '1';--控制SN74LVC4245,DIR=1,信号流向:A->B
data_outctl <= (not cpld_cs) and (not rd) and wr;--判断读时序
data_out <= data_buf when(data_outctl='1') else "00000000";--如果是读时序则输出数据到FSMC总线
process(cpld_rest)
begin
if(cpld_rest = '0') then
data_buf <= x"18";--x代表16进制数,如果复位键按下,则输出缓冲的数据为0x18
else
data_buf <= x"58";
end if;
end process;
end architecture behav;
管脚锁定图示:
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