新唐MS51基于1T的8051微控制器datasheet

只看该作者 · 2023-8-10 16:12

MS51是一个嵌入式闪存型，8位高性能的基于1T的8051微控制器。该指令集与标准的80C51完全兼容，并且性能得到了增强。
主闪存的 MS51 8KB 字节称为 APROM，用户代码的内容位于其中。 MS51 闪存支持在应用程序编程 (IAP) 功能，可实现片上固件更新。 IAP 还可以配置用户代码数组的任何块用作非易失性数据存储，由 IAP 写入并由 IAP 或 MOVC 指令读取，此功能意味着整个 8K Bytes 区域都可以用作数据闪存通过 IAP 命令。 MS51 支持从称为 LDROM 的 APROM 中配置闪存的功能，引导代码通常驻留在其中以执行在系统编程 (ISP)。 LDROM 大小可通过 CONFIG 定义配置为最大 4K 字节。还有一个额外的包括特殊的 128 字节安全保护内存 (SPROM) 以增强客户应用程序的安全性和保护。为了便于编程和验证，Flash 允许通过并行写入器或在线编程 (ICP) 进行电子编程和读取。密码确认后，用户可以锁定密码以确保安全。
MS51 提供丰富的外围设备，包括 256 字节的 SRAM、1K 字节的辅助 RAM (XRAM)、多达 12 个通用 I/O、两个 16 位定时器/计数器 0/1、一个具有三通道输入的 16 位定时器 2 捕获模块，1个看门狗定时器（WDT），1个自唤醒定时器（WKT），1个通用或波特率发生器的16位自动重载Timer3，2个带帧错误检测和自动地址识别的UART，1个SPI，一个 I2C、五个增强型 PWM 输出通道、所有 I/O 的八通道共享引脚中断和一个 12 位 ADC。外围设备配备 18 个具有 4 级优先级中断能力的源。
MS51 配备三个时钟源，并支持通过软件进行即时切换。三个时钟源包括外部时钟输入、10 kHz 内部振荡器和一个 16 MHz 内部精密振荡器，该振荡器在出厂时已在室温下调整为 ±1%。 MS51 提供额外的电源监控检测，例如上电复位和 4 级欠压检测，可稳定高可靠性系统设计的电源开/关顺序。
MS51 微控制器运行功耗极低，有两种经济功耗模式可降低功耗——空闲模式和掉电模式，可通过软件选择。空闲模式关闭 CPU 时钟但允许继续外设操作。掉电模式停止整个系统时钟以实现最低功耗。 MS51 的系统时钟也可以通过软件时钟分频器减慢，从而在执行性能和功耗之间实现灵活性。
凭借高性能 CPU 内核和丰富的精心设计的外围设备，MS51 有利于满足通用、家用电器或电机控制系统的要求。

2 特点

Core and System
8051	 Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51.  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs).
Power On Reset (POR)	 POR with 1.15V threshold voltage level
Brown-out Detector (BOD)	 4-level selection, with brown-out interrupt and reset option. (4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)	 LVR with 2.0V threshold voltage level
Security	 96-bit Unique ID (UID)  128-bit Unique Customer ID (UCID)  128-bytes security protection memory SPROM
Memories
Flash	 8 KBytes of APROM for User Code.  4/3/2/1 Kbytes of Flash for loader (LDROM) configure from APROM for In-System-Programmable (ISP)  Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-Programmable (IAP) means whole APROM can be use as Data Flash  An additional 128 bytes security protection memory SPROM  Code lock for security by CONFIG
SRAM	 256 Bytes on-chip RAM.  Additional 1 KBytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction.
Clocks
Internal Clock Source	 Default 16 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V).  Selectable 24 MHz high-speed internal oscillator (HIRC).  10 kHz low-speed internal oscillator (LIRC) calibrating to ±1% by software from high-speed internal oscillator
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\clip_image2.pngTimers
16-bit Timer	 Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer2 with three-channel input capture module and 9 input pin can be selected.  One 16-bit auto-reload Timer3, which can be the baud rate clock source of UART0 and UART1.
Watchdog	 6-bit free running up counter for WDT time-out interval.  Selectable time-out interval is 6.40 ms ~ 1.638s since WDT_CLK = 10 kHz (LIRC).  Able to wake up from Power-down or Idle mode  Interrupt or reset selectable on watchdog time-out
Wake-up Timer	 16-bit free running up counter for time-out interval.  Clock sources from LIRC  Able self Wake-up wake up from Power-down or Idle mode, and auto reload count value.  Supports Interrupt
PWM	 Up To 5 channel output pins can be selected  Supports maximum clock source frequency up to 24 MHz  Supports independent mode for PWM output  Supports complementary mode for up to 2 complementary paired PWM output channels  Dead-time insertion with 8-bit resolution  Supports 16-bit resolution PWM counter  Supports mask function and tri-state enable for each PWM pin  Supports brake function  Supports trigger ADC on the following events
Analog Interfaces
	 Analog input voltage range: 0 ~ AVDD.
	 12-bit resolution and 10-bit accuracy is guaranteed.
	 Up to 7 single-end analog input channels
Analog-to-Digital Converter (ADC)	 1 internal channels, they are band-gap voltage (VBG).  Up to 500 ksps sampling rate.
	 Software Write 1 to ADCS bit.
	 External pin (STADC) trigger
	 PWM trigger.
Communication Interfaces
UART	 Supports up to 2 UARTs: UART0 & UART1
	 Full-duplex asynchronous communications  Programmable 9th bit.  UART0_TXD and UART0_RXD pins exchangeable via software.
I2C	 1 set of I2C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  7-bit addressing mode  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  Supports hold time programmable
SPI	 1 set of SPI devices  Supports Master or Slave mode operation  Supports MSB first or LSB first transfer sequence  slave mode up to 12 MHz
GPIO	 Four I/O modes: – Quasi-bidirectional mode – Push-Pull Output mode – Open-Drain Output mode – Input only with high impendence mode  Schmitt trigger input / TTL mode selectable.  Each I/O pin configured as interrupt source with edge/level trigger setting  Standard interrupt pins I̅ ̅̅̅T̅̅0̅ and I̅ ̅̅̅T̅̅1̅.  Supports high drive and high sink current I/O  I/O pin internal pull-up or pull-down resistor enabled in input mode.  Maximum I/O Speed is 24 MHz  Each GPIO enabling the pin interrupt function will also enable the wake-up function
ESD & EFT
ESD	 HBM pass 8 kV
EFT	 > ± 4.4 kV
Latch-up	 150 mA pass

5.1 MS51 8KB 系列框图
图 5.1-1 显示了 MS51 的功能框图并给出了器件的外形。用户可以在图中找到设备的所有外围功能。

MS51是一个嵌入式闪存型，8位高性能的基于1T的8051微控制器。该指令集与标准的80C51完全兼容，并且性能得到了增强。
主闪存的 MS51 8KB 字节称为 APROM，用户代码的内容位于其中。 MS51 闪存支持在应用程序编程 (IAP) 功能，可实现片上固件更新。 IAP 还可以配置用户代码数组的任何块用作非易失性数据存储，由 IAP 写入并由 IAP 或 MOVC 指令读取，此功能意味着整个 8K Bytes 区域都可以用作数据闪存通过 IAP 命令。 MS51 支持从称为 LDROM 的 APROM 中配置闪存的功能，引导代码通常驻留在其中以执行在系统编程 (ISP)。 LDROM 大小可通过 CONFIG 定义配置为最大 4K 字节。还有一个额外的包括特殊的 128 字节安全保护内存 (SPROM) 以增强客户应用程序的安全性和保护。为了便于编程和验证，Flash 允许通过并行写入器或在线编程 (ICP) 进行电子编程和读取。密码确认后，用户可以锁定密码以确保安全。
MS51 提供丰富的外围设备，包括 256 字节的 SRAM、1K 字节的辅助 RAM (XRAM)、多达 12 个通用 I/O、两个 16 位定时器/计数器 0/1、一个具有三通道输入的 16 位定时器 2 捕获模块，1个看门狗定时器（WDT），1个自唤醒定时器（WKT），1个通用或波特率发生器的16位自动重载Timer3，2个带帧错误检测和自动地址识别的UART，1个SPI，一个 I2C、五个增强型 PWM 输出通道、所有 I/O 的八通道共享引脚中断和一个 12 位 ADC。外围设备配备 18 个具有 4 级优先级中断能力的源。
MS51 配备三个时钟源，并支持通过软件进行即时切换。三个时钟源包括外部时钟输入、10 kHz 内部振荡器和一个 16 MHz 内部精密振荡器，该振荡器在出厂时已在室温下调整为 ±1%。 MS51 提供额外的电源监控检测，例如上电复位和 4 级欠压检测，可稳定高可靠性系统设计的电源开/关顺序。
MS51 微控制器运行功耗极低，有两种经济功耗模式可降低功耗——空闲模式和掉电模式，可通过软件选择。空闲模式关闭 CPU 时钟但允许继续外设操作。掉电模式停止整个系统时钟以实现最低功耗。 MS51 的系统时钟也可以通过软件时钟分频器减慢，从而在执行性能和功耗之间实现灵活性。
凭借高性能 CPU 内核和丰富的精心设计的外围设备，MS51 有利于满足通用、家用电器或电机控制系统的要求。

2 特点

Core and System
8051	 Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51.  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs).
Power On Reset (POR)	 POR with 1.15V threshold voltage level
Brown-out Detector (BOD)	 4-level selection, with brown-out interrupt and reset option. (4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)	 LVR with 2.0V threshold voltage level
Security	 96-bit Unique ID (UID)  128-bit Unique Customer ID (UCID)  128-bytes security protection memory SPROM
Memories
Flash	 8 KBytes of APROM for User Code.  4/3/2/1 Kbytes of Flash for loader (LDROM) configure from APROM for In-System-Programmable (ISP)  Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-Programmable (IAP) means whole APROM can be use as Data Flash  An additional 128 bytes security protection memory SPROM  Code lock for security by CONFIG
SRAM	 256 Bytes on-chip RAM.  Additional 1 KBytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction.
Clocks
Internal Clock Source	 Default 16 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V).  Selectable 24 MHz high-speed internal oscillator (HIRC).  10 kHz low-speed internal oscillator (LIRC) calibrating to ±1% by software from high-speed internal oscillator
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\clip_image2.pngTimers
16-bit Timer	 Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer2 with three-channel input capture module and 9 input pin can be selected.  One 16-bit auto-reload Timer3, which can be the baud rate clock source of UART0 and UART1.
Watchdog	 6-bit free running up counter for WDT time-out interval.  Selectable time-out interval is 6.40 ms ~ 1.638s since WDT_CLK = 10 kHz (LIRC).  Able to wake up from Power-down or Idle mode  Interrupt or reset selectable on watchdog time-out
Wake-up Timer	 16-bit free running up counter for time-out interval.  Clock sources from LIRC  Able self Wake-up wake up from Power-down or Idle mode, and auto reload count value.  Supports Interrupt
PWM	 Up To 5 channel output pins can be selected  Supports maximum clock source frequency up to 24 MHz  Supports independent mode for PWM output  Supports complementary mode for up to 2 complementary paired PWM output channels  Dead-time insertion with 8-bit resolution  Supports 16-bit resolution PWM counter  Supports mask function and tri-state enable for each PWM pin  Supports brake function  Supports trigger ADC on the following events
Analog Interfaces
	 Analog input voltage range: 0 ~ AVDD.
	 12-bit resolution and 10-bit accuracy is guaranteed.
	 Up to 7 single-end analog input channels
Analog-to-Digital Converter (ADC)	 1 internal channels, they are band-gap voltage (VBG).  Up to 500 ksps sampling rate.
	 Software Write 1 to ADCS bit.
	 External pin (STADC) trigger
	 PWM trigger.
Communication Interfaces
UART	 Supports up to 2 UARTs: UART0 & UART1
	 Full-duplex asynchronous communications  Programmable 9th bit.  UART0_TXD and UART0_RXD pins exchangeable via software.
I2C	 1 set of I2C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  7-bit addressing mode  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  Supports hold time programmable
SPI	 1 set of SPI devices  Supports Master or Slave mode operation  Supports MSB first or LSB first transfer sequence  slave mode up to 12 MHz
GPIO	 Four I/O modes: – Quasi-bidirectional mode – Push-Pull Output mode – Open-Drain Output mode – Input only with high impendence mode  Schmitt trigger input / TTL mode selectable.  Each I/O pin configured as interrupt source with edge/level trigger setting  Standard interrupt pins I̅ ̅̅̅T̅̅0̅ and I̅ ̅̅̅T̅̅1̅.  Supports high drive and high sink current I/O  I/O pin internal pull-up or pull-down resistor enabled in input mode.  Maximum I/O Speed is 24 MHz  Each GPIO enabling the pin interrupt function will also enable the wake-up function
ESD & EFT
ESD	 HBM pass 8 kV
EFT	 > ± 4.4 kV
Latch-up	 150 mA pass