根据 RM0313~233
sdac通断控制
通过在SDADC_CR2寄存器中设置ADON位来启用saddc。SDADC上电后，需要100 us稳定才能开始转换或发射校准(除非PDI=1，请参见下一节)。在此期间请求的操作将在稳定完成后自动启动。稳定结束由SDAC_ISR寄存器中的STABIP位表示。
清除ADON将停止任何可能正在进行的转换，并将SDADC置于断电模式。
The sequence of injected conversions executing in continuous mode can be stopped by writing to the JONT bit. After clearing the JCONT bit, only the on-going conversion will be completed; the scan sequence is interrupted, and thus the final conversion will not be the last(highest)selected channel unless it was the one being converted when the JCONT bit was cleared.
Similarly, writing to the RCONT bit stops continuous regular conversions, allowing only the currently executing conversion to complete.
If just a single channel is selected in continuous mode(either by executing a regular conversion or by executing a injected conversion with only one channel selected), the sampling rate can be increased three fold by setting the FAST bit in the SDADCCR2 register. The conversion of each channel normally requires 360 SDADC clock cycles(60 us at 6 MHZ). In fast continuous mode(FAST=1), the first conversion takes still 360 SDADC clocks, but then each subsequent conversion finishes in 120 SDADC clocks.
在连续模式下执行的注入转换序列可以通过向JCONT位写入’0’来停止。清除JCONT位后，只完成正在进行的转换;扫描序列被中断，因此最后的转换将不是最后(最高)选择的通道，除非它是在JcONT位被清除时被转换的通道。
类似地，将’0’写入RCONT位将停止连续的规则转换，只允许当前正在执行的转换完成。
如果在连续模式下只选择一个通道(通过执行常规转换或通过执行仅选择一个通道的注入转换)，通过在SDADC_CR2寄存器中设置FAST位，采样率可以增加三倍。每个通道的转换通常需要360个SDADC时钟周期(6 MHz时60 us)。在快速连续模式下(fast =1)，第一次转换仍然需要360个sadc时钟，但随后的每次转换在120个sadc时钟中完成。
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版权声明：本文为CSDN博主「明东(Maxwell)」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/Maxwell_321/article/details/130708944
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