HotCRC CRC8L_07_00_00 FPGA模块 HotPower@163.com（菜农独创）

/*-----------------------------------------------------------------------------------------------

      HotCRC CRC8L_07_00_00 FPGA模块 HotPower[url=home.php?mod=space&uid=516618]@163.com[/url] 2023-09-21 10:38:58

-----------------------------------------------------------------------------------------------*/

module CRC8L_07(clk, rst, data, outcrc8)

input clk, rst;

input [7:0] data;

output reg[7:0] outcrc8;

reg [7:0] crc8;



task CRC8L_07;

inout[7:0] crc8;

input[7:0] indata;

    crc8 = CRC8L_07_Table(crc8 ^ indata);

endtask



function [7:0] CRC8L_07_Table;

    input [7:0] data;

    CRC8L_07_Table = CRC8L_07_Table0(data[1:0]) ^ CRC8L_07_Table1(data[3:2]) ^ CRC8L_07_Table2(data[5:4]) ^ CRC8L_07_Table3(data[7:6]);

endfunction



function [7:0] CRC8L_07_Table0;

    input[1:0] data;

    case(data)

        2'b00: CRC8L_07_Table0 = 8'h00; 2'b01: CRC8L_07_Table0 = 8'h07; 2'b10: CRC8L_07_Table0 = 8'h0E; 2'b11: CRC8L_07_Table0 = 8'h09;

        default: CRC8L_07_Table0 = 8'h00;

    endcase

endfunction



function [7:0] CRC8L_07_Table1;

    input[1:0] data;

    case(data)

        2'b00: CRC8L_07_Table1 = 8'h00; 2'b01: CRC8L_07_Table1 = 8'h1C; 2'b10: CRC8L_07_Table1 = 8'h38; 2'b11: CRC8L_07_Table1 = 8'h24;

        default: CRC8L_07_Table1 = 8'h00;

    endcase

endfunction



function [7:0] CRC8L_07_Table2;

    input[1:0] data;

    case(data)

        2'b00: CRC8L_07_Table2 = 8'h00; 2'b01: CRC8L_07_Table2 = 8'h70; 2'b10: CRC8L_07_Table2 = 8'hE0; 2'b11: CRC8L_07_Table2 = 8'h90;

        default: CRC8L_07_Table2 = 8'h00;

    endcase

endfunction



function [7:0] CRC8L_07_Table3;

    input[1:0] data;

    case(data)

        2'b00: CRC8L_07_Table3 = 8'h00; 2'b01: CRC8L_07_Table3 = 8'hC7; 2'b10: CRC8L_07_Table3 = 8'h89; 2'b11: CRC8L_07_Table3 = 8'h4E;

        default: CRC8L_07_Table3 = 8'h00;

    endcase

endfunction





always @(posedge clk or negedge rst)

begin

    if (!rst)

    begin

        crc8 <= 8'h00;

    end

    else

    begin

        CRC8L_0(crc8, data);

        outcrc8 <= crc8;

        crc8 <= crc8;

    end

end

endmodule