本帖最后由 pigedong 于 2023-10-26 15:28 编辑
我按AT415的DEMO工程调试4路PWM输出，发现通道2的占空比不对，不管设置为多少，输出都为7%，其他3路正常
void pwm_init(void)
{
gpio_init_type gpio_init_struct;
tmr_output_config_type tmr_output_struct;
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_TMR2_PERIPH_CLOCK, TRUE);
/* set default parameter */
gpio_default_para_init(&gpio_init_struct);
/* time2 output pin configuration */
gpio_init_struct.gpio_pins = GPIO_PINS_0 | GPIO_PINS_1 | GPIO_PINS_2 | GPIO_PINS_3;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
/* get system clock */
//crm_clocks_freq_get(&crm_clocks_freq_struct);
//nvic_irq_enable(TMR2_GLOBAL_IRQn, 0, 0);
/* compute the value to be set in arr regist to generate frequency at 20KHz */
prescaler =0;
timer_period = (144000000 / 20000)-1;
/* compute ccr1 value to generate a duty at 50% for channel 1 and 1n */
channel1_pulse = (uint16_t) (((uint32_t)33 * (timer_period - 1)) / 100);
/* compute ccr1 value to generate a duty at 50% for channel 1 and 1n */
channel2_pulse = (uint16_t) (((uint32_t)75 * (timer_period - 1)) / 100);
/* compute ccr1 value to generate a duty at 50% for channel 1 and 1n */
channel3_pulse = (uint16_t) (((uint32_t)75 * (timer_period - 1)) / 100);
/* compute ccr1 value to generate a duty at 12.5% for channel 1 and 1n */
channel4_pulse = (uint16_t) (((uint32_t)50 * (timer_period - 1)) / 100);
/* tmr2 time base configuration */
tmr_base_init(TMR2, timer_period, prescaler);
tmr_cnt_dir_set(TMR2, TMR_COUNT_UP);
/* channel 1, 2, 3 and 4 configuration in output mode */
tmr_output_default_para_init(&tmr_output_struct);
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
tmr_output_struct.oc_output_state = TRUE;
tmr_output_struct.oc_idle_state = FALSE;
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_output_channel_config(TMR2, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
tmr_channel_value_set(TMR2, TMR_SELECT_CHANNEL_1, channel2_pulse);
tmr_output_channel_config(TMR2, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
tmr_channel_value_set(TMR2, TMR_SELECT_CHANNEL_2, channel2_pulse);
tmr_output_channel_config(TMR2, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
tmr_channel_value_set(TMR2, TMR_SELECT_CHANNEL_3, channel3_pulse);
tmr_output_channel_config(TMR2, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
tmr_channel_value_set(TMR2, TMR_SELECT_CHANNEL_4, channel4_pulse);
/* tmr2 int enable */
//tmr_interrupt_enable(TMR2, TMR_C1_INT | TMR_C2_INT | TMR_C3_INT | TMR_C4_INT, TRUE);
/* tmr2 output enable */
tmr_output_enable(TMR2, TRUE);
/* tmr2 enable counter */
tmr_counter_enable(TMR2, TRUE);
} |
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