STM32 - 定时器的设定

只看该作者 · 2023-11-24 00:30

基础- 0D - Timer synchronization & chaining - 主从模式下 - 定时器同步和级联控制 - 级联启动定时器

和前面两次举例不同的是，前面两次是用CC通道的输出波形来做触发，这个例子，用UEV的发生做触发：

In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 140 for connections. Timer 2 starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer 1. When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).

• Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register).

控制模式选择器：

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

• Configure the Timer 1 period (TIM1_ARR registers).

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). 连接T1

• Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).

只看该作者 · 2023-11-24 00:30

从模式选择器：

Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.

010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.

011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

只看该作者 · 2023-11-24 00:30

只看该作者 · 2023-11-24 00:31

只看该作者 · 2023-11-24 00:31

As in the previous example, the user can initialize both counters before starting counting.

Figure 144 shows the behavior with the same configuration as in Figure 143 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register).

只看该作者 · 2023-11-24 00:31

Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to Figure 140 for connections. To ensure the counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2):

• Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).

只看该作者 · 2023-11-24 00:31

Counter Enable 输出为触发信号

只看该作者 · 2023-11-24 00:32

当CNT_EN做触发输入的时候，在TRGO触发有一个Delay。

• Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the TIM1_SMCR register).

只看该作者 · 2023-11-24 00:32

Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).

只看该作者 · 2023-11-24 00:32

Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).

只看该作者 · 2023-11-24 00:32

这个MSM非常重要，他可以允许时间Delay 来匹配当前的Timer（即使是主Timer）来和从Timer进行信号同步。

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

只看该作者 · 2023-11-24 00:33

只看该作者 · 2023-11-24 00:33

• Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).

只看该作者 · 2023-11-24 00:33

When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1.