void spi_dma_config()
{
rcu_periph_clock_enable(RCU_DMA1);
spi_dma_enable(SPI2_ARM_DSP, SPI_DMA_TRANSMIT);
spi_dma_enable(SPI2_ARM_DSP, SPI_DMA_RECEIVE);
dma_interrupt_enable(DMA1, DMA_CH0, DMA_INT_FTF); // 通道传输完成
dma_parameter_struct dma_init_struct;
// 发送dma
dma_deinit(DMA1, DMA_CH1);
dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI2);
dma_init_struct.memory_addr = (uint32_t)&spi2_send_array;
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
dma_init_struct.priority = DMA_PRIORITY_LOW;
dma_init_struct.number = 1;
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init(DMA1, DMA_CH1, &dma_init_struct);
dma_circulation_disable(DMA1, DMA_CH1);
dma_memory_to_memory_disable(DMA1, DMA_CH1);
dma_channel_enable(DMA1, DMA_CH1);
// 接收dma
dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI2);
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_HIGH;
dma_init_struct.number = 1;
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_addr = (uint32_t)&spi2_recv_array;
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_deinit(DMA1, DMA_CH0);
dma_init(DMA1, DMA_CH0, &dma_init_struct);
dma_circulation_disable(DMA1, DMA_CH0);
dma_memory_to_memory_disable(DMA1, DMA_CH0);
dma_channel_enable(DMA1, DMA_CH0);
}
void DMA1_Channel0_IRQHandler(void)
{
if (SET == dma_interrupt_flag_get(DMA1, DMA_CH0, DMA_INT_FLAG_FTF))
{
dma_interrupt_flag_clear(DMA1, DMA_CH0, DMA_INT_FLAG_FTF);
//
}
}
void nvic_config(void)
{
nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0);
// NVIC_SetPriority(SysTick_IRQn, 0x00U);
// nvic_irq_enable(SysTick_IRQn, 0, 0);
nvic_irq_enable(TIMER2_IRQn, 12, 0);
nvic_irq_enable(CAN0_RX0_IRQn, 14, 0);
nvic_irq_enable(CAN1_RX0_IRQn, 15, 0);
nvic_irq_enable(RTC_IRQn, 8, 0);
nvic_irq_enable(USART0_IRQn, 2, 0);
nvic_irq_enable(USART1_IRQn, 1, 0);
// nvic_irq_enable(USART2_IRQn, 2, 0);
// nvic_irq_enable(UART3_IRQn, 3, 0);
can_interrupt_enable(CAN0, CAN_INT_RFNE0);
can_interrupt_enable(CAN1, CAN_INT_RFNE0);
nvic_irq_enable(SPI0_IRQn, 4, 0);
nvic_irq_enable(SPI1_IRQn, 5, 0);
nvic_irq_enable(SPI2_IRQn, 6, 0);
nvic_irq_enable(DMA1_Channel0_IRQn, 0, 0);
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